TSMC under triple pressure: customer diversification, patent challenges, and EUV strategy shift
Summary
Key Takeaways
TSMC faces an unprecedented confluence of operational, legal, and commercial pressures. Google is in talks to split production of its next-generation AI chip Icefish: TSMC for the core logic in 1.4nm, Samsung for memory I/O, with mass production no earlier than 2028—a clear signal that even the most loyal customer seeks alternatives.
The US ITC is investigating patent complaints by Longitude Licensing and Marlin Semiconductor against TSMC, alleging unauthorized advanced manufacturing technology. A preliminary ruling is expected June 2026, final by October. With North America accounting for ~75% of TSMC's revenue, an import ban on affected chips would be devastating.
Chairman Wei Zhejia warns that skilled worker shortages are the biggest bottleneck, along with water, electricity, land, and talent. TSMC's 3nm monthly capacity reaches 175,000 wafers but still undersupplied; prices will rise up to 15% in H2 2026. Advanced packaging CoWoS is booked through next year.
TSMC confirms it will not buy ASML's high-NA EUV tools (~$400M each) before 2029, instead using multi-patterning on existing low-NA EUV for 2nm, saving an estimated $5-10 billion in capex.
Why It Matters
TSMC's public stance is fundamentally defensive against Samsung and Intel poaching orders. Google splitting Icefish signals a zero-trust move away from single-supplier dependency. Skipping high-NA EUV saves capex but multi-patterning increases process complexity, risking yield loss and longer lead times—hidden costs for customers.
Patent litigation is a lock-in weapon: if ITC restricts imports, AI chip supply chains (NVIDIA, AMD, Google TPU) face disruption, forcing multi-sourcing. TSMC's price hikes and CoWoS congestion directly raise AI chip TCO for enterprise deployments.
The EUV route reveals technology dependency risk: low-NA multi-patterning at 2nm may suffer from tail latency and yield issues compared to high-NA single exposure, impacting HPC chip efficiency and reliability.
PRO Decision
【Vendors】 Samsung and Intel should exploit TSMC's bottlenecks and patent risks, aggressively pitch their foundry and advanced packaging (e.g., Samsung's 3nm GAA, Intel's 18A) to Google, AMD, NVIDIA, emphasizing supply chain resilience and offering benchmark comparisons against TSMC's multi-patterning yield risks.
【Enterprises】 CIOs must immediately audit single-supplier dependency on TSMC, demand roadmap alternatives from chip vendors (Samsung, Intel foundry). Monitor TSMC's 2nm yield data and lead times; incorporate supplier concentration risk into AI infrastructure TCO models.
【Investors】 See through TSMC's PR: patent litigation and customer diversification are structural threats. Skipping high-NA EUV saves capex but may erode competitiveness at sub-2nm nodes, opening doors for Samsung and Intel. Consider reducing TSMC positions, increasing Samsung and ASML (high-NA EUV demand delayed but inevitable).
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