Reports
AI-generated structured vendor updates
TSMC Develops quasi-EMIB Packaging to Break CoWoS Capacity Bottleneck
TSMC is collaborating with Kinsus to develop quasi-EMIB advanced packaging to address severe CoWoS capacity constraints. The new approach aims to simplify manufacturing, reduce cycle time, and lower costs, bolstering TSMC's competitive position against Intel and Samsung.
TSMC Develops EMIB-Like Packaging with Kinsus to Counter Intel's CoWoS Threat
TSMC, in response to CoWoS capacity constraints and potential customer loss, is developing an EMIB-like advanced packaging technology with Kinsus, aiming to simplify manufacturing steps and reduce costs, preventing clients from shifting to Intel's packaging platform, highlighting the strategic importance of advanced packaging in AI chip competition.
TSMC Accelerates 1.4nm Process, Partners with Unimicron on EMIB-Like Packaging to Counter Intel
TSMC accelerates its 1.4nm (A14) process to mid-2028 mass production, using second-gen GAA NanoFlex Pro transistors and existing EUV lithography. It also partners with Unimicron on EMIB-like packaging to alleviate CoWoS capacity constraints and prevent AI chip customer loss to Intel's packaging platform.
TSMC Develops EMIB-like Packaging to Challenge Intel and Ease CoWoS Bottleneck
TSMC is developing an EMIB-like advanced packaging technology that uses small silicon bridges instead of large silicon interposers, reducing cost and complexity while easing CoWoS capacity constraints. This move counters Intel's EMIB technology and addresses the growing packaging demands of AI accelerators, securing TSMC's dominance in advanced packaging.
Intel Accelerates 14A to 2027H2 Risk Production, 18A Yield Exceeds Target by 25%, Capex Raised to $20B
Intel announced 14A process acceleration to risk production in 2027H2 with HVM in 2028, 18A yield exceeding target by 25% supporting Panther Lake volume, and raising 2026 capex to $20B, signaling an aggressive foundry push. Advanced packaging EMIB-T becomes a profit pillar.
AMD Unveils Zen 6 Venice, MI455X, and Helios Rack-Level Design to Challenge NVIDIA
At Advancing AI 2026, AMD launched Zen 6 EPYC Venice (2nm, up to 256 cores) and MI455X (CDNA5, 432GB HBM4, 40 PFLOPS FP4), along with Helios rack reference design (2.9 exaFLOPS FP4 per rack), claiming a 1000x AI performance roadmap, with major commitments from Meta, OpenAI, and others.
TSMC Q1 Earnings: Advanced Packaging Capacity Bottleneck to Persist, Constraining AI Chip Supply Through 2025
TSMC Q1 earnings show HPC crossing 60% revenue share for the first time; CoWoS advanced packaging capacity will remain tight through 2027—the real AI chip supply bottleneck is packaging, not processes.
Intel Foundry Breakthrough: EMIB Packaging Gains Strategic Endorsement from Google, Amazon
The strategic significance of this deal far exceeds surface numbers. Google's and Amazon's simultaneous shift to Intel signals: US cloud giants' strategic consensus on 'de-TSMC-ization' in AI chips has formed. Not just chip manufacturing, but advanced packaging—high-value-added manufacturing—is also undergoing supply chain restructuring.