TSMC
2026-07-30
TSMC Develops EMIB-like Packaging to Challenge Intel and Ease CoWoS Bottleneck
Summary
Key Takeaways
According to The Information, TSMC is developing an advanced packaging technology that rivals Intel's EMIB (Embedded Multi-die Interconnect Bridge), internally called EMIB-like technology. Unlike traditional CoWoS-S which uses a large silicon interposer to connect processor dies and HBM, the EMIB-like approach employs small silicon bridges embedded only at chip boundaries where high interconnect density is needed, avoiding the cost of full silicon interposer. This design significantly reduces packaging cost and complexity while alleviating CoWoS capacity constraints.
The development is driven by severe capacity shortages in TSMC's advanced packaging. TSMC CEO C.C. Wei admitted that CoWoS capacity is limiting customer expansion. Reports indicate that Google and other customers evaluated Intel EMIB as an alternative, prompting TSMC to accelerate its own solution to maintain market dominance. Intel's EMIB directly embeds silicon bridges in the substrate for high-speed die-to-die interconnects, eliminating the need for a separate large interposer. NVIDIA is reportedly evaluating Intel EMIB for a four-chip integrated next-generation processor.
Following the news, TSMC stock rose ~8.5%, and Intel stock rose ~13%, reflecting positive market sentiment. Advanced packaging has become a critical bottleneck for AI chip manufacturing. As AI accelerators integrate more cores and HBM in larger packages, packaging technology directly determines performance, cost, and delivery. TSMC's move signals that packaging has evolved from a back-end step to a strategic competitive differentiator.
Why It Matters
On the surface, TSMC's EMIB-like technology aims to ease CoWoS capacity constraints, but it is fundamentally a defensive move against Intel's EMIB encroaching on its advanced packaging dominance, while also containing Samsung and other competitors. By developing its own silicon bridge solution, TSMC seeks to lock customers into its packaging ecosystem and prevent defection to Intel or Samsung.
However, TSMC may downplay the engineering limitations. Unlike Intel's mature EMIB, TSMC's version is still under development, with unproven yield, interconnect density, and signal integrity. The small silicon bridge reduces interposer cost but may introduce parasitic effects and thermal management issues, potentially impacting tail latency and bandwidth density in multi-die AI accelerators. Moreover, this technology may not scale for future HBM4 interfaces, as bridge density may lag behind full interposer TSV solutions. Customers should be wary of being locked into a single-vendor packaging roadmap with uncertain long-term scalability.
PRO Decision
[Vendors] Intel should aggressively ramp up EMIB capacity and highlight its maturity and performance advantages to NVIDIA and other customers, while pointing out the unproven yield and engineering risks of TSMC's EMIB-like solution, aiming to capture high-end AI chip packaging orders. Intel could also open its packaging as a standalone service to attract more AI chip designers and break TSMC's monopoly.
[Enterprises] CIOs and architects should incorporate packaging supplier concentration risk into procurement evaluations, requiring chip suppliers to disclose packaging technology roadmaps and multi-sourcing strategies. For mission-critical AI deployments, consider Intel EMIB-based chips as a second source to hedge against TSMC capacity constraints.
[Investors] Recognize that TSMC's move is defensive, reflecting severe CoWoS bottlenecks. The EMIB-like technology faces uncertain development timelines and may not alleviate capacity shortages soon. Intel's packaging competitiveness could reshape the AI chip supply chain, potentially eroding TSMC's packaging monopoly. Monitor Intel's customer adoption and TSMC's ability to maintain its packaging moat.
Get 3-5 key AI infrastructure signals weekly →
💬 Comments (0)