Reports
AI-generated structured vendor updates
OpenAI and Broadcom Unveil Jalapeno Inference ASIC, Reshaping AI Hardware Landscape
OpenAI, in collaboration with Broadcom, has developed Jalapeno, a custom LLM inference accelerator. The chip uses a multi-chip module with HBM3E memory and achieved tape-out in just nine months. Designed for OpenAI's model stack, it aims to reduce inference costs and dependency on NVIDIA GPUs, with initial deployment planned for late 2026.
TSMC Hikes Advanced Node Prices 5-10%, Squeezing AI Chip Margins
TSMC informs clients of 5-10% price hikes across all advanced nodes (7nm+), affecting 74% of wafer revenue. Apple, Nvidia, AMD, and others face higher costs, potentially raising AI infrastructure prices.
SK hynix Files for $29B Nasdaq IPO to Fund AI Memory Fabs and EUV Tools
SK hynix files for a $29.4B ADR listing on Nasdaq, with proceeds earmarked for its Yongin fab, Cheongju HBM packaging plant, and ASML EUV scanners. New capacity won't arrive until 2027, but the move solidifies its 57% HBM market share and locks in critical EUV supply.
ASML CEO Validates Musk's Terafab, Reshaping AI Chip Supply Chain
ASML's CEO publicly acknowledges tracking Elon Musk's planned terawatt-scale AI supercomputer Terafab, comparing it to Korean DRAM megaprojects. This signals that the sole EUV lithography supplier is allocating capacity, potentially transforming AI chip supply chain and vertical integration.
TSMC under triple pressure: customer diversification, patent challenges, and EUV strategy shift
TSMC faces operational, legal, and commercial pressures: Google splits Icefish AI chip production with Samsung, US ITC patent probe risks import bans, and resource bottlenecks (labor, water, power) limit expansion. TSMC confirms it will skip high-NA EUV until 2029, using multi-patterning on low-NA EUV for 2nm, saving $5-10B.
ASML EXE:5200 High-NA EUV: 8nm Resolution Locks 2nm Node, Cost Trap Looms
ASML launches the EXE:5200 High-NA EUV lithography system, boosting resolution from 13nm to 8nm and wafer throughput to 220 WPH, enabling 2nm and beyond. Intel is the first customer for its 18A process. ASML also reveals Hyper-NA (NA 0.85) development for sub-1nm nodes.
Nvidia's Grid Integration Play: Locking AI Customers via Energy Control Against Hyperscaler Rivals
Nvidia is pivoting from chip seller to grid-integrated AI factory developer, building a 96MW facility in Virginia using Vera Rubin DSX design to directly respond to electricity markets. This move aims to lock customers via energy infrastructure, countering Google TPU and Amazon Trainium. It also raised $25B in bonds, investing in battery startup Verse to bypass grid connection delays.
Odyssey's $310M Pivot to Trainium Signals Control Shift from Nvidia to AWS Silicon
World-model startup Odyssey raised $310M Series B at $1.45B valuation, naming AWS preferred cloud with Trainium chips. After taking Nvidia's money in Series A, Nvidia is absent this round—a clear signal that AI startups are pivoting away from Nvidia GPU lock-in toward Amazon/AMD alternative silicon.
ASML CEO's EUV Supply Warning Signals a Physical Ceiling on AI Chip Expansion
ASML CEO Fouquet confirms talks with Musk on Terafab but stresses supply constraints. EUV lithography, the sole tool for advanced AI chips, cannot scale quickly. With TSMC, Samsung, Intel, and Musk all vying for limited machines, AI chip capacity allocation becomes a zero-sum game, capping the entire AI infrastructure buildout.
Huawei's LogicFolding: 3D Stacking Rewrites AI Chip Rules
Huawei's Tau Scaling Law and LogicFolding architecture boost transistor density by 55% and power efficiency by 41% via vertical logic stacking, targeting 1.4nm-class by 2031. Ascend 920/910C chips are now used for DeepSeek V4-Pro post-training, signaling real-world AI workload deployment and challenging Nvidia's dominance in China.
ASML, TSMC, imec Demo 300mm 2D-Material Transistors at 50nm Pitch
imec, ASML, and TSMC demonstrate the first 300mm wafer integration of MoS2/WS2/WSe2-based n and pFETs with 50nm contacted poly pitch (CPP) using single-patterning EUV lithography, achieving 94% operational yield. This lab-to-fab breakthrough paves the way for 2D channel materials to extend Moore's Law.
ASML扩大风险投资布局，加强欧洲半导体和深科技生态系统
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Huawei's Tao Law: LogicFolding Bypasses Lithography, 55% Density Gain on Fixed Node
At ISCAS 2026, Huawei's He Tingbo unveiled the Tao Law, replacing geometric scaling with temporal optimization targeting tau (characteristic time). LogicFolding vertically stacks active layers to shorten critical paths, achieving 55% transistor density increase and 41% energy efficiency gain on a fixed node. Kirin 2026 reaches 3.1GHz; Ascend series will adopt LogicFolding. The roadmap projects equivalent 1.4nm density by 2031, fundamentally challenging Moore's Law's lithography dependency.
Seven European Tech Giants Issue Joint Call for EU Reform to Safeguard Tech Sovereignty
CEOs of seven leading European tech companies, including ASML, Airbus, Ericsson, and Mistral AI, co-signed an open letter urging the EU to simplify digital regulations and reform competition policy. This aims to accelerate the scaling of next-gen technologies like industrial AI in Europe to enhance global competitiveness.
ASML Integrates Lithography and Metrology Systems in Semiconductor Manufacturing Ecosystem
ASML has built an integrated product matrix centered on lithography systems, combined with metrology and computational lithography. Its EUV and DUV scanners support advanced chip manufacturing, while YieldStar metrology and Tachyon software enable process optimization and yield control. This forms a complete semiconductor manufacturing toolchain from patterning to process control.
ASML Technology Overview: The Core of Semiconductor Manufacturing from Lithography to Metrology
ASML, a global leader in semiconductor equipment, centers its technology portfolio around the core process of lithography. This brief highlights its three key technological pillars: Lithography, Metrology & Inspection, and Computational Lithography. In lithography, ASML offers a full range from Deep Ultraviolet (DUV) to Extreme Ultraviolet (EUV) solutions. Its EUV lithography machines, utilizing 13.5-nanometer wavelength light, are critical for manufacturing advanced logic and memory chips. The technology generates plasma light by firing a high-power laser at tin droplets, coupled with precision optics and vacuum systems for nanoscale patterning. For metrology and inspection, ASML employs tools like HMI e-beam metrology to perform nanoscale inspection of post-lithography wafers for pattern fidelity, overlay accuracy, and defects, providing essential data for process control. Computational lithography, via the Tachyon software platform, uses complex algorithms and massive computing power to model and optimize between chip design (mask) and physical manufacturing. This compensates for physical effects during lithography to ensure final wafer pattern accuracy. These three technologies work in close synergy, forming a complete technological loop from design to manufacturing.
ASML System Integration Innovation Strengthens Semiconductor Manufacturing Tech Barrier
ASML drives EUV and High-NA technology through deep integration of lithography hardware, metrology systems, and computational lithography software. This systemic innovation enhances chip manufacturing precision and yield, strengthening its leadership in advanced processes.
ASML Advances Lithography Paradigm Shift Through Computational Patterning
ASML integrates EUV lithography with computational patterning techniques (OPC, SMO, Multi-Beam) to systematically optimize imaging chains and push k1 factor beyond physical limits. This represents a paradigm shift from hardware-driven advances to hardware-algorithm fusion, enabling more economical chip scaling.
ASML Unveils Lithography Accuracy Measurement Technology: The Key to Nanometer Control
ASML has published a technical article detailing the critical principles of "measuring accuracy" in its lithography technology. The article states that in chip manufacturing, lithography machines must transfer circuit patterns onto silicon wafers with extreme precision, and measurement is the foundation for achieving this accuracy. ASML ensures precision through its unique "alignment" and "overlay" measurement systems. The alignment system ensures precise alignment between the silicon wafer and the mask, while overlay measurement is used to assess the pattern registration accuracy between consecutive lithography layers, which is crucial for manufacturing complex 3D structures. ASML's technology can achieve sub-nanometer measurement accuracy, a core capability that continuously drives the miniaturization of chip processes (such as the evolution towards 3nm nodes and beyond). This technology is an indispensable part of ASML's advanced equipment like Extreme Ultraviolet (EUV) lithography machines, ensuring consistency and yield in mass production. **Comment**: By delving into its fundamental measurement technology, ASML once again highlights its technical moat in the semiconductor equipment field. Sub-nanometer measurement and control capabilities are the invisible cornerstone enabling the continuation of Moore's Law. For chip manufacturers and material/metrology equipment suppliers, paying attention to the evolution of such underlying precision technologies is key to anticipating the feasibility and challenges of advanced process node implementation.
ASML Discloses Core Precision Mechatronics Technology in Lithography Systems
ASML detailed the precision mechatronics foundation of its lithography systems, including ultra-precision motion control platforms, active vibration isolation, and advanced sensor feedback loops. These technologies enable nanometer-scale chip manufacturing accuracy and highlight critical system-level engineering capabilities.