TSMC
2026-06-30
TSMC, ASML, imec Demonstrate 300mm 2D Material CMOS with 50nm CPP, 94% Yield
Summary
Key Takeaways
At VLSI 2026, imec, ASML, and TSMC jointly demonstrated the first industrial-scale 300mm wafer 2D material transistor integration process. Key achievements include:
- First 50nm contacted poly pitch (CPP) for 2D material nFET (MoS₂) and pFET (WS₂/WSe₂), with ultra-low off-state leakage (Imax/Imin > 10⁵) and 94% yield.
- Optimized single-exposure EUV lithography with ASML enabled 28nm channel length, meeting advanced node requirements.
- Successful CMOS-like integration of nFET and pFET on the same 300mm wafer, demonstrating 2D materials' superior electrostatic control and mobility at scaled dimensions, positioning them as a silicon replacement candidate.
Why It Matters
This demonstration by TSMC/ASML/imec is a strategic move to defend against Intel and Samsung in advanced nodes and lock-in the 2D material supply chain around ASML's EUV. It creates a full-stack barrier from material to lithography to integration, forcing competitors to either adopt ASML tools or pursue alternative routes like CFET.
However, the announcement downplays critical engineering limitations:
- Large-area uniformity: 2D materials (MoS₂, WS₂) suffer from high defect density and thickness variation over 300mm wafers; 94% yield likely reflects small-scale tests.
- Contact resistance: Metal-2D material contacts exhibit much higher resistance than silicon, causing RC delay and power penalty, especially at 28nm channel length.
- Reliability: Poor thermal conductivity of 2D materials leads to localized heating under high current density; no reliability data was disclosed.
- Cost trap: EUV single exposure masks process complexity but 2D material CVD growth and transfer remain expensive; High-NA EUV depreciation will further increase TCO.
PRO Decision
【Vendors (Intel, Samsung, GlobalFoundries)】 Immediately launch independent 2D material alternative routes, focusing on backside power delivery (BSPDN) and CFET architectures to avoid TSMC-ASML's EUV+2D lock-in. Partner with Applied Materials, KLA to develop non-EUV 2D lithography (e.g., nanoimprint) to break ASML's monopoly.
【Enterprises (chip buyers, cloud providers)】 No short-term procurement change needed, but demand reliability data (TDDB, HCI, BTI) and mass production timeline from TSMC. Build cross-node supply risk assessment to prevent exclusive advanced process dependency on TSMC's 2D technology.
【Investors】 Be aware that TSMC's R&D spending may surge (2D tools, process development), but success could solidify its foundry leadership. Watch for accelerated ASML High-NA EUV orders and imec's 2D material patent portfolio. Stay cautious on Intel and Samsung's advanced node investments as they may need to catch up on 2D materials.
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