Reports
AI-generated structured vendor updates
ASML高数值孔径EUV光刻机实现量产就绪新里程碑
...
TSMC Accelerates 1.4nm Process, Partners with Unimicron on EMIB-Like Packaging to Counter Intel
TSMC accelerates its 1.4nm (A14) process to mid-2028 mass production, using second-gen GAA NanoFlex Pro transistors and existing EUV lithography. It also partners with Unimicron on EMIB-like packaging to alleviate CoWoS capacity constraints and prevent AI chip customer loss to Intel's packaging platform.
TSMC 2nm Volume Production Begins, AMD First to Launch Venice and MI455X
TSMC has fully ramped its 2nm process at five fabs, contributing ~3% of wafer revenue in Q2. AMD launches the first 2nm-based products: EPYC Venice (256 cores) and Instinct MI455X (320B transistors, 432GB HBM4), shipping in Q3. Samsung targets 1.4nm by 2029, Intel 18A introduces High-NA EUV, intensifying foundry competition.
ASML Q2营收93亿欧元 High-NA EUV在Intel 18A达到生产级良率
...
NVIDIA Prepay $1.5B to Amkor for US 2nm/3nm/HBM4 Advanced Packaging
NVIDIA prepays $1.5B to Amkor to expand advanced packaging capacity in Arizona, covering 2nm/3nm/HBM4. This onshores AI chip packaging, complementing Wistron's system integration, to reduce reliance on Taiwan and secure supply for Vera Rubin and Blackwell Ultra.
Intel Accelerates 14A to 2027H2 Risk Production, 18A Yield Exceeds Target by 25%, Capex Raised to $20B
Intel announced 14A process acceleration to risk production in 2027H2 with HVM in 2028, 18A yield exceeding target by 25% supporting Panther Lake volume, and raising 2026 capex to $20B, signaling an aggressive foundry push. Advanced packaging EMIB-T becomes a profit pillar.
IBM Unveils 0.7nm Nanostack 3D Transistor, Doubling Density and Extending Moore’s Law
IBM debuts the world’s first sub-1nm chip technology at 0.7nm node using a nanostack 3D transistor architecture, packing nearly 100 billion transistors with double the density of its 2nm node. It delivers 50% performance gain or 70% energy efficiency improvement, and 40% SRAM scaling for AI workloads.
AMD Confirms Zen 6 EPYC Venice: First 2nm Server CPU Launching July 2026
AMD confirms Zen 6 EPYC Venice launch at Advancing AI 2026 (July 22-23). As the first 2nm server CPU, it features triple-core hybrid architecture, up to 192 cores, ~29% single-thread and ~22% multi-thread gains, targeting AI inference and tight CPU-GPU synergy via Infinity Fabric.
TSMC Hikes Sub-7nm Prices 8-12%, Extends Lead Times to 26 Weeks, Triggering AI Chip Cost Inflation
TSMC raises sub-7nm wafer prices by 8-12% and extends lead times to 26 weeks, effective July 2026. New v2.1 directive mandates EDA tool validation for PDK access. This directly inflates AI chip TCO, delays new product launches, and solidifies TSMC's control over the AI supply chain.
Huawei Unveils Tao's Law V2: Kirin 2026 Boosts AI Inference 40% on Same Node
Huawei's He Tingbo releases Tao's Law V2, detailing Kirin 2026 metrics: 238 MTr/mm² transistor density (+55%), 41% power reduction at iso-performance, and 40% SRAM frequency increase. Without EUV lithography, co-optimization of architecture, circuit, and process delivers equivalent performance gains, proving system-level optimization as a viable alternative to Moore's Law scaling.
Samsung Restarts 1.4nm Foundry Node, Pre-emptively Locks Equipment Supply Chain
Samsung Electronics restarts 1.4nm (SF1.4) process commercialization, ordering equipment vendors to develop tools early. The node will use High-NA EUV lithography and GAA transistors, fabbed at NRD-K campus. This move aims to catch up with TSMC and Intel, but mass production timeline remains undisclosed.
Samsung Re-accelerates 1.4nm Node R&D, Adopts High-NA EUV Lithography
Samsung Electronics is re-accelerating its 1.4nm (SF1.4) process node R&D, targeting mass production by 2028-2029. It has procured High-NA EUV lithography equipment from ASML for its NRD-K R&D complex and ordered tools for 12th-gen V-NAND with wafer stacking. The move aims to catch up with TSMC and Intel in the AI chip foundry race.
TSMC, ASML, imec Demonstrate 300mm 2D Material CMOS with 50nm CPP, 94% Yield
TSMC, ASML, and imec jointly demonstrated the first 300mm wafer-scale integration of 2D material transistors at VLSI 2026, achieving 50nm contacted poly pitch (CPP) for MoS₂ nFET and WS₂/WSe₂ pFET with 28nm channel length and 94% yield, marking a critical step toward industrializing 2D semiconductors.
Qualcomm Dragonfly: 250-core CPU, HBC memory, UALink interconnects target AI inference TCO
Qualcomm unveils full data center portfolio: Dragonfly C1000 250-core Oryon CPU (>5GHz, PCIe Gen7, CXL), HBC near-memory compute (133TB/s Gen1, 18x-54x effective BW), AI300 inference accelerator (UALink/ESUN scale-up), and 800G/1.6T connectivity. Multi-year Meta CPU deal. Commercial sampling 2027-2028. Targets inference TCO with tokens-per-watt leadership.
OpenAI and Broadcom Unveil Jalapeno Inference ASIC, Reshaping AI Hardware Landscape
OpenAI, in collaboration with Broadcom, has developed Jalapeno, a custom LLM inference accelerator. The chip uses a multi-chip module with HBM3E memory and achieved tape-out in just nine months. Designed for OpenAI's model stack, it aims to reduce inference costs and dependency on NVIDIA GPUs, with initial deployment planned for late 2026.
TSMC Hikes Advanced Node Prices 5-10%, Squeezing AI Chip Margins
TSMC informs clients of 5-10% price hikes across all advanced nodes (7nm+), affecting 74% of wafer revenue. Apple, Nvidia, AMD, and others face higher costs, potentially raising AI infrastructure prices.
ASML CEO Validates Musk's Terafab, Reshaping AI Chip Supply Chain
ASML's CEO publicly acknowledges tracking Elon Musk's planned terawatt-scale AI supercomputer Terafab, comparing it to Korean DRAM megaprojects. This signals that the sole EUV lithography supplier is allocating capacity, potentially transforming AI chip supply chain and vertical integration.
TSMC under triple pressure: customer diversification, patent challenges, and EUV strategy shift
TSMC faces operational, legal, and commercial pressures: Google splits Icefish AI chip production with Samsung, US ITC patent probe risks import bans, and resource bottlenecks (labor, water, power) limit expansion. TSMC confirms it will skip high-NA EUV until 2029, using multi-patterning on low-NA EUV for 2nm, saving $5-10B.
ASML EXE:5200 High-NA EUV: 8nm Resolution Locks 2nm Node, Cost Trap Looms
ASML launches the EXE:5200 High-NA EUV lithography system, boosting resolution from 13nm to 8nm and wafer throughput to 220 WPH, enabling 2nm and beyond. Intel is the first customer for its 18A process. ASML also reveals Hyper-NA (NA 0.85) development for sub-1nm nodes.
ASML CEO's EUV Supply Warning Signals a Physical Ceiling on AI Chip Expansion
ASML CEO Fouquet confirms talks with Musk on Terafab but stresses supply constraints. EUV lithography, the sole tool for advanced AI chips, cannot scale quickly. With TSMC, Samsung, Intel, and Musk all vying for limited machines, AI chip capacity allocation becomes a zero-sum game, capping the entire AI infrastructure buildout.