Reports
AI-generated structured vendor updates
TSMC's 5.5-Reticle CoWoS Hits 99% Yield, 14x Roadmap Redefines AI Chip Integration
TSMC announced 5.5-reticle CoWoS yield exceeding 98% (up to 99%) at OCP APAC Summit, with a roadmap to 14-reticle by 2029 integrating 10 compute dies and 20 HBM stacks. SoIC hybrid bonding improves interconnect density by 50x and energy efficiency by 5x, solidifying TSMC's lead in advanced packaging.
TSMC 3nm Capacity Expansion Accelerates: Q4 Target 180K Wafers Per Month
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Microsoft's Maia 200 Chip: A Giant Leap for AI Processing
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TSMC targets 100,000 monthly 2nm wafers by 2026, fueled by AI demand
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MediaTek sees SerDes 448G as copper's final battleground
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MediaTek Advances CoWoS, EMIB-T and 3.5D Packaging Strategy
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TSMC Accelerates 1.4nm Production, Develops EMIB-like Packaging to Rival Intel
TSMC accelerates its 1.4nm (A14) process to trial production in Q3 2027, using second-gen GAA nanosheet transistors with 20-23% density improvement. It also develops an EMIB-like advanced packaging to counter Intel's EMIB-T, aiming to retain AI chip packaging business.
Intel EMIB-T Packaging Claims 50% Cost Edge Over TSMC CoWoS, Aims for 2027
Intel's EMIB-T packaging achieves ~50% cost reduction vs TSMC CoWoS by eliminating silicon interposer. With yields approaching 90%, volume production slated for 2027, potentially disrupting AI chip packaging market.
TSMC Accelerates 1.4nm Process, Partners with Unimicron on EMIB-Like Packaging to Counter Intel
TSMC accelerates its 1.4nm (A14) process to mid-2028 mass production, using second-gen GAA NanoFlex Pro transistors and existing EUV lithography. It also partners with Unimicron on EMIB-like packaging to alleviate CoWoS capacity constraints and prevent AI chip customer loss to Intel's packaging platform.
TSMC Develops EMIB-like Packaging to Challenge Intel and Ease CoWoS Bottleneck
TSMC is developing an EMIB-like advanced packaging technology that uses small silicon bridges instead of large silicon interposers, reducing cost and complexity while easing CoWoS capacity constraints. This move counters Intel's EMIB technology and addresses the growing packaging demands of AI accelerators, securing TSMC's dominance in advanced packaging.
Qualcomm Accelerates Data Center Shift with HBC Integrated Chip, Apple Modem Loss Spurs Pivot
Qualcomm Q3 results reveal Apple modem revenue set to drop 50% QoQ, accelerating its data center pivot. First HBC (compute+memory integrated packaging) chip taped out, targeting $15B DC revenue by FY2029. Also announces broad price hike from Sep 1.
NVIDIA Rubin GPU Detailed: 3nm Dual-Die, 336B Transistors, 288GB HBM4, NVLink 6 Doubles Bandwidth
NVIDIA unveiled the full Rubin GPU architecture at SIGGRAPH 2026: 3nm dual-die, 336B transistors, 288GB HBM4 with 22 TB/s bandwidth, and NVLink 6 at 3600 GB/s. The NVL72 rack integrates 72 GPUs with 36 Vera CPUs, requiring full liquid cooling due to >1000W TDP.
NVIDIA Vera Rubin NVL72 Enters Production, 10x Energy Efficiency Reshapes AI Infrastructure
NVIDIA has announced full production of the Vera Rubin NVL72 platform, with first shipments to CoreWeave, Microsoft, Amazon, and Oracle. Each rack integrates 72 Rubin GPUs and 36 Vera CPUs, delivering 10x improvement in energy efficiency and inference cost over Blackwell for agentic AI workloads, marking a new era of rack-scale AI infrastructure.
TSMC 2nm Volume Production Begins, AMD First to Launch Venice and MI455X
TSMC has fully ramped its 2nm process at five fabs, contributing ~3% of wafer revenue in Q2. AMD launches the first 2nm-based products: EPYC Venice (256 cores) and Instinct MI455X (320B transistors, 432GB HBM4), shipping in Q3. Samsung targets 1.4nm by 2029, Intel 18A introduces High-NA EUV, intensifying foundry competition.
高通第六代骁龙8系列将涨价，2纳米制程推高成本
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AMD Helios Enters Production: 12-Stack HBM4 Outmuscles NVIDIA, UALoE Opens AI Network
AMD's second-generation Helios rack-scale AI server enters full production, featuring 72 MI455X GPUs with Samsung's exclusive 12-stack HBM4 (31TB per rack). Compared to NVIDIA's 8-stack design, it offers 50% more memory and 30% lower token cost. Microsoft Azure commits to large-scale deployment, solidifying hyperscaler dual-vendor strategy.
Meta Transforms into AI Compute Landlord with $10B Anthropic Lease Deal
Meta is in early talks with Anthropic for a $10 billion compute lease deal, marking its strategic shift from internal AI infrastructure user to commercial landlord. This move monetizes Meta's massive capex and creates an inter-cloud leasing model, fundamentally reshaping the AI compute supply chain.
NVIDIA Prepay $1.5B to Amkor for US 2nm/3nm/HBM4 Advanced Packaging
NVIDIA prepays $1.5B to Amkor to expand advanced packaging capacity in Arizona, covering 2nm/3nm/HBM4. This onshores AI chip packaging, complementing Wistron's system integration, to reduce reliance on Taiwan and secure supply for Vera Rubin and Blackwell Ultra.
Intel Accelerates 14A to 2027H2 Risk Production, 18A Yield Exceeds Target by 25%, Capex Raised to $20B
Intel announced 14A process acceleration to risk production in 2027H2 with HVM in 2028, 18A yield exceeding target by 25% supporting Panther Lake volume, and raising 2026 capex to $20B, signaling an aggressive foundry push. Advanced packaging EMIB-T becomes a profit pillar.
NVIDIA and Wistron Launch US-Based GB300 Production, Shifting AI Manufacturing Landscape
NVIDIA partnered with Wistron to open a $700M factory in Texas, achieving L6 integration of the GB300 Grace Blackwell Ultra system. The first US-made unit contains 1.5M parts, weighs 2 tons, and costs $4M. This milestone accelerates US AI capex localization from 5% to 30%, reshaping the global AI supply chain.