TSMC
2026-08-02
TSMC Develops quasi-EMIB Packaging to Break CoWoS Capacity Bottleneck
Summary
Key Takeaways
TSMC's CoWoS advanced packaging capacity is severely constrained, becoming a key bottleneck for AI accelerators like NVIDIA H100/B200. Meanwhile, Intel's EMIB is gaining traction due to its flexibility and shorter cycle times. To stay competitive, TSMC is internally developing quasi-EMIB, an EMIB-like embedded bridge solution optimized for its manufacturing, aiming to simplify steps, reduce cycle time, and lower cost. Compared to CoWoS-S and CoWoS-L, quasi-EMIB may trade off some interconnect density for higher throughput. TSMC is partnering with Kinsus, a substrate manufacturer, for this project. This move signals TSMC's aggressive response to Intel and Samsung in advanced packaging, potentially reshaping the supply chain.
Why It Matters
TSMC's quasi-EMIB is a defensive move against Intel's EMIB, but it risks locking customers into a new design flow with potential performance compromises. For high-end AI chips like NVIDIA H100, quasi-EMIB may offer lower interconnect density and thermal performance compared to CoWoS-S/L. Additionally, reliance on Kinsus for substrates introduces new supply chain risks, as ABF substrate capacity is already tight.
PRO Decision
【Vendors】Intel should highlight EMIB's maturity and performance in high-end AI chips, and expand capacity to capture TSMC's customers. Samsung can promote its I-Cube packaging and multi-foundry strategy to reduce lock-in. 【Enterprises】CIOs should demand packaging transparency from chip vendors, evaluate performance implications, and avoid single-source packaging dependency. 【Investors】Recognize quasi-EMIB as a defensive move; monitor customer adoption and Kinsus' capacity. TSMC's packaging diversification is positive long-term but may pressure margins.
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