Reports
AI-generated structured vendor updates
MediaTek pivots to datacenter AI, targets 15-20% share with advanced packaging and 448G SerDes
MediaTek announced a $5B flexible financing framework to expand its AI chip business, raising its 2027 datacenter AI accelerator target market share to 15-20%. It is advancing CoWoS, EMIB-T, and 3.5D packaging, planning 448G SerDes, copper co-package, and CPO technologies, and preparing two generations of custom AI accelerator ASICs.
TSMC's 5.5-reticle CoWoS Hits 99% Yield, Targets 14x Reticle by 2029
TSMC announced at OCP APAC that its 5.5-reticle CoWoS has entered mass production with >99% yield. It plans to scale to 14x reticle by 2028, enabling integration of ~10 compute dies and 20 HBM stacks, dramatically boosting AI chip density.
MediaTek Advances CoWoS, EMIB-T and 3.5D Packaging Strategy
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MediaTek Adopts Dual Packaging: CoWoS and Intel EMIB-T for ASIC
MediaTek CEO confirms ASIC projects adopt Intel EMIB-T packaging alongside TSMC CoWoS. EMIB-T uses micro bridges for high-density interconnects, supporting HBM, achieving 8-10x reticle area at lower cost. Dual-track strategy highlights packaging as a key competitive dimension in AI chips.
TSMC Accelerates 1.4nm Production, Develops EMIB-like Packaging to Rival Intel
TSMC accelerates its 1.4nm (A14) process to trial production in Q3 2027, using second-gen GAA nanosheet transistors with 20-23% density improvement. It also develops an EMIB-like advanced packaging to counter Intel's EMIB-T, aiming to retain AI chip packaging business.
Intel EMIB-T Packaging Claims 50% Cost Edge Over TSMC CoWoS, Aims for 2027
Intel's EMIB-T packaging achieves ~50% cost reduction vs TSMC CoWoS by eliminating silicon interposer. With yields approaching 90%, volume production slated for 2027, potentially disrupting AI chip packaging market.
TSMC Develops quasi-EMIB Packaging to Break CoWoS Capacity Bottleneck
TSMC is collaborating with Kinsus to develop quasi-EMIB advanced packaging to address severe CoWoS capacity constraints. The new approach aims to simplify manufacturing, reduce cycle time, and lower costs, bolstering TSMC's competitive position against Intel and Samsung.
Intel Accelerates Ohio Fab, Plans 14A by 2031, EMIB-T Packaging 50% Cheaper than CoWoS but Yield at 50%
Intel is accelerating its Ohio fab construction, targeting 14A process mass production by 2031. Its EMIB-T advanced packaging offers 50% cost reduction over TSMC CoWoS, but substrate yield remains at 50%, limiting scale-up. EMIB-T packaging service expected by 2027.
TSMC Develops EMIB-Like Packaging with Kinsus to Counter Intel's CoWoS Threat
TSMC, in response to CoWoS capacity constraints and potential customer loss, is developing an EMIB-like advanced packaging technology with Kinsus, aiming to simplify manufacturing steps and reduce costs, preventing clients from shifting to Intel's packaging platform, highlighting the strategic importance of advanced packaging in AI chip competition.
TSMC Accelerates 1.4nm Process, Partners with Unimicron on EMIB-Like Packaging to Counter Intel
TSMC accelerates its 1.4nm (A14) process to mid-2028 mass production, using second-gen GAA NanoFlex Pro transistors and existing EUV lithography. It also partners with Unimicron on EMIB-like packaging to alleviate CoWoS capacity constraints and prevent AI chip customer loss to Intel's packaging platform.
TSMC Develops EMIB-like Packaging to Challenge Intel and Ease CoWoS Bottleneck
TSMC is developing an EMIB-like advanced packaging technology that uses small silicon bridges instead of large silicon interposers, reducing cost and complexity while easing CoWoS capacity constraints. This move counters Intel's EMIB technology and addresses the growing packaging demands of AI accelerators, securing TSMC's dominance in advanced packaging.
Intel’s U.S. Advanced Packaging Enables Next-Generation AI Semiconductors - Intel Newsroom
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Intel Accelerates 14A to 2027H2 Risk Production, 18A Yield Exceeds Target by 25%, Capex Raised to $20B
Intel announced 14A process acceleration to risk production in 2027H2 with HVM in 2028, 18A yield exceeding target by 25% supporting Panther Lake volume, and raising 2026 capex to $20B, signaling an aggressive foundry push. Advanced packaging EMIB-T becomes a profit pillar.
Intel Foundry 18A Yields Jump to 85%+; EMIB Packaging Hits 98%, Challenging TSMC N2
Intel Foundry 18A yields surged from 65% to 85%+ in a single quarter, approaching TSMC N2's 90%. EMIB advanced packaging yields reached 90-98%, turning a former bottleneck into a selling point. NVIDIA, AMD, Apple signed on but mostly as secondary suppliers.
Intel 18A Yield Hits 85%, Secures Orders from NVIDIA, OpenAI, Reshaping Foundry Landscape
Intel reports 18A process yield improvement to 85%, from 65% last quarter, nearing TSMC N2's 90%. Secured foundry deals with NVIDIA, AMD, OpenAI, etc. EMIB advanced packaging yield reaches 98%, used in NVIDIA Feynman, Google TPU. This marks a strategic inflection in AI chip manufacturing.
Intel押注3D堆叠AI芯片 18A-PT+Foveros Direct 3D+EMIB-T全栈整合
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Intel Foundry Lands Google TPU Packaging Deal: EMIB-T Shakes TSMC's AI Chip Monopoly
Intel secures a multi-billion-dollar deal to package over 3 million Google TPUs using its advanced EMIB-T 2.5D packaging, while the chips themselves remain fabricated at TSMC. This marks Intel's strategic shift from CPU vendor to second-source AI packaging partner, targeting 2028 production. Intel's 18A node yields exceed expectations, but analysts caution the scope is limited to packaging.
Google Awards 3M+ TPU Packaging Orders to Intel Foundry, Breaking TSMC's CoWoS Monopoly
Google has awarded Intel Foundry over 3 million units of next-gen TPU advanced packaging orders, leveraging Intel's EMIB technology with production starting in 2028. This marks Intel Foundry's largest external customer win and a pivotal shift in AI chip packaging away from TSMC's CoWoS monopoly.
Huawei's Tao Law: LogicFolding Bypasses Lithography, 55% Density Gain on Fixed Node
At ISCAS 2026, Huawei's He Tingbo unveiled the Tao Law, replacing geometric scaling with temporal optimization targeting tau (characteristic time). LogicFolding vertically stacks active layers to shorten critical paths, achieving 55% transistor density increase and 41% energy efficiency gain on a fixed node. Kirin 2026 reaches 3.1GHz; Ascend series will adopt LogicFolding. The roadmap projects equivalent 1.4nm density by 2031, fundamentally challenging Moore's Law's lithography dependency.
Intel Foundry Breakthrough: EMIB Packaging Gains Strategic Endorsement from Google, Amazon
The strategic significance of this deal far exceeds surface numbers. Google's and Amazon's simultaneous shift to Intel signals: US cloud giants' strategic consensus on 'de-TSMC-ization' in AI chips has formed. Not just chip manufacturing, but advanced packaging—high-value-added manufacturing—is also undergoing supply chain restructuring.