Reports
AI-generated structured vendor updates
台积电四季度3纳米月产能预计达18万片
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TSMC 3nm Capacity Expansion Accelerates: Q4 Target 180K Wafers Per Month
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MediaTek Advances CoWoS, EMIB-T and 3.5D Packaging Strategy
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MediaTek Adopts Dual Packaging: CoWoS and Intel EMIB-T for ASIC
MediaTek CEO confirms ASIC projects adopt Intel EMIB-T packaging alongside TSMC CoWoS. EMIB-T uses micro bridges for high-density interconnects, supporting HBM, achieving 8-10x reticle area at lower cost. Dual-track strategy highlights packaging as a key competitive dimension in AI chips.
Intel EMIB-T Packaging Claims 50% Cost Edge Over TSMC CoWoS, Aims for 2027
Intel's EMIB-T packaging achieves ~50% cost reduction vs TSMC CoWoS by eliminating silicon interposer. With yields approaching 90%, volume production slated for 2027, potentially disrupting AI chip packaging market.
TSMC Develops quasi-EMIB Packaging to Break CoWoS Capacity Bottleneck
TSMC is collaborating with Kinsus to develop quasi-EMIB advanced packaging to address severe CoWoS capacity constraints. The new approach aims to simplify manufacturing, reduce cycle time, and lower costs, bolstering TSMC's competitive position against Intel and Samsung.
Intel Accelerates Ohio Fab, Plans 14A by 2031, EMIB-T Packaging 50% Cheaper than CoWoS but Yield at 50%
Intel is accelerating its Ohio fab construction, targeting 14A process mass production by 2031. Its EMIB-T advanced packaging offers 50% cost reduction over TSMC CoWoS, but substrate yield remains at 50%, limiting scale-up. EMIB-T packaging service expected by 2027.
TSMC Develops EMIB-Like Packaging with Kinsus to Counter Intel's CoWoS Threat
TSMC, in response to CoWoS capacity constraints and potential customer loss, is developing an EMIB-like advanced packaging technology with Kinsus, aiming to simplify manufacturing steps and reduce costs, preventing clients from shifting to Intel's packaging platform, highlighting the strategic importance of advanced packaging in AI chip competition.
TSMC Accelerates 1.4nm Process, Partners with Unimicron on EMIB-Like Packaging to Counter Intel
TSMC accelerates its 1.4nm (A14) process to mid-2028 mass production, using second-gen GAA NanoFlex Pro transistors and existing EUV lithography. It also partners with Unimicron on EMIB-like packaging to alleviate CoWoS capacity constraints and prevent AI chip customer loss to Intel's packaging platform.
TSMC Develops EMIB-like Packaging to Challenge Intel and Ease CoWoS Bottleneck
TSMC is developing an EMIB-like advanced packaging technology that uses small silicon bridges instead of large silicon interposers, reducing cost and complexity while easing CoWoS capacity constraints. This move counters Intel's EMIB technology and addresses the growing packaging demands of AI accelerators, securing TSMC's dominance in advanced packaging.
NVIDIA Vera Rubin NVL72 Enters Production, 10x Energy Efficiency Reshapes AI Infrastructure
NVIDIA has announced full production of the Vera Rubin NVL72 platform, with first shipments to CoreWeave, Microsoft, Amazon, and Oracle. Each rack integrates 72 Rubin GPUs and 36 Vera CPUs, delivering 10x improvement in energy efficiency and inference cost over Blackwell for agentic AI workloads, marking a new era of rack-scale AI infrastructure.
NVIDIA Prepay $1.5B to Amkor for US 2nm/3nm/HBM4 Advanced Packaging
NVIDIA prepays $1.5B to Amkor to expand advanced packaging capacity in Arizona, covering 2nm/3nm/HBM4. This onshores AI chip packaging, complementing Wistron's system integration, to reduce reliance on Taiwan and secure supply for Vera Rubin and Blackwell Ultra.
AMD Helios Rack Challenges NVIDIA NVLink with Open UALoE Interconnect
At Advancing AI 2026, AMD launched the Helios rack with 72 MI455X GPUs, 18 Venice EPYC CPUs, and Pensando networking, claiming 30% higher inference token/$ vs NVIDIA NVL72. It introduced UALoE open interconnect to break NVLink lock-in, partnering with Cerebras, Cisco, and major AI firms.
NVIDIA-OpenAI $100B Partnership: 10GW Vera Rubin AI Factories Reshape Ecosystem
NVIDIA and OpenAI announce a strategic partnership to deploy at least 10GW of NVIDIA systems using the Vera Rubin platform (Rubin GPU, Vera CPU, HBM4, NVLink 6). NVIDIA will invest up to $100B. First facilities go online in H2 2026, powering OpenAI's next-gen models, marking the era of multi-GW AI factories.
NVIDIA Reveals Vera Rubin GPU and Vera CPU: 3360B Transistors, 88-Core Olympus, 10x Agentic AI Efficiency
NVIDIA fully discloses Vera Rubin GPU and Vera CPU specifications. The GPU features 3360B transistors, HBM4 288GB, and 10x agentic AI efficiency over Blackwell. The CPU has 88 custom Olympus cores, delivering 2.2x faster agentic AI performance than Intel Sapphire Rapids. This solidifies NVIDIA's full-stack strategy against x86 incumbents.
TSMC Pledges $100B More for 6 US Fabs, Localizing 3nm for AI Chip Supply Chain
TSMC announces an additional $100B investment in Arizona, bringing total US commitment to $265B, with plans for 6 fabs focused on 3nm and beyond. This move localizes advanced process for AI chip demand from NVIDIA, Apple, AMD, reshaping global semiconductor supply chain. Q2 net profit surged 77% YoY, FY capex raised to $60-64B.
JCET's $1.4B AI Packaging Capex Reshapes Advanced Packaging Supply Chain
JCET announces $1.4B capex for AI advanced packaging in 2026, targeting Chiplet, HBM, 2.5D/3D. This marks Chinese OSAT's major entry into high-end packaging, complementing TSMC's CoWoS expansion and shifting AI packaging from Taiwan-centric to cross-strait division, supporting local hyperscalers' computing needs.
TSMC CoWoS Capacity to Reach 200k Wafers by 2027, Diversifying from GPU to CPU and ASIC
TSMC targets 200k wpm CoWoS capacity by 2027, narrowing supply-demand gap from 20% to 10%. Customer base diversifies from NVIDIA GPU to include AI server CPUs (MediaTek, AMD) and ASICs (Broadcom). CoPoS panel-level packaging enters pilot production in 2027.
Intel押注3D堆叠AI芯片 18A-PT+Foveros Direct 3D+EMIB-T全栈整合
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TSMC Hikes Advanced Node Prices 5-10%, Squeezing AI Chip Margins
TSMC informs clients of 5-10% price hikes across all advanced nodes (7nm+), affecting 74% of wafer revenue. Apple, Nvidia, AMD, and others face higher costs, potentially raising AI infrastructure prices.