Architecture Shift
Impact: important
Strength: High
TSMC 2026 Roadmap: No High-NA EUV Through 2029
Summary
TSMC unveiled 2029 roadmap on April 22: A12/A13 skip High-NA EUV. Dual-track: client nodes annually, AI/HPC biennially. A16 delayed to 2027, A12/A13 in 2029. CoWoS expanding to 14-reticle (2028) and 40-reticle (2029).
Key Takeaways
TSMC SVP Kevin Zhang: "Our R&D has been exceptionally effective in pushing current EUV capabilities while maintaining an aggressive scaling roadmap. This is definitely an advantage. Perhaps one day they will have to use high-NA, but for now we can still fully leverage existing EUV technology without switching to high-NA — which is very, very expensive." High-NA EUV costs $400M/unit, roughly double current EUV. TSMC achieved 30x EUV wafer output increase and 24% power reduction through proprietary EUV pellicle (outperforming ASML originals), AI computational lithography (cuLitho 40x speedup), multi-patterning, and source power increases. ASML shares fell 3.7%; its High-NA plan for 2027-2028 mass production and €60B revenue by 2030 faces revision. TechInsights Dan Hutcheson: "Advanced packaging is displacing lithography as the key enabler of density gains."
Why It Matters
Scaling drivers shifting from lithography upgrades to optimization + advanced packaging. Hits ASML revenue expectations; Intel/Samsung gain differentiation but bear higher capex risk; A16 delay impacts AI chip roadmaps.
PRO Decision
Chip designers: IP compatibility reduces migration cost, but A16 delay requires roadmap re-evaluation. ASML: invest more in source power and yield tools. Investors: short-term margin benefit, long-term High-NA transition risk.
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