Reports
AI-generated structured vendor updates
NVIDIA & SK hynix Deepen Memory Co-Engineering: Custom HBM for Vera Rubin and Jetson Thor
NVIDIA and SK hynix have announced a multiyear partnership to co-develop next-generation custom memory for NVIDIA's AI factory ecosystem, including Vera Rubin supercomputers, Vera CPUs, RTX Spark PCs, and Jetson Thor robotic platforms. SK hynix will also use NVIDIA CUDA-X libraries and Omniverse to accelerate semiconductor design and build fab digital twins.
AMD, Dell, Cambridge Launch UK Sovereign AI Lab to Challenge NVIDIA's CUDA Dominance with Open ROCm
AMD, Dell, and the University of Cambridge launch the Sovereign AI Innovation Lab (SAIL) in the UK, deploying Zenith supercomputer with 5th Gen EPYC and Instinct MI355X GPUs, plus the Sunrise fusion AI system. The lab promotes open, interoperable AI infrastructure based on AMD ROCm, challenging NVIDIA's CUDA lock-in and offering long-term technology choice for national AI initiatives.
AMD EPYC Challenges Rack-Scale Density for Agentic AI Control
AMD claims its EPYC processors lead in rack-scale performance for agentic AI's CPU-intensive services (orchestration, caching, databases). Under a 100kW rack model, EPYC 9965 'Turin' delivers 2.37x throughput over NVIDIA Vera, with next-gen 'Venice' projected at 3.30x. Emphasizes deployability on current x86 platforms, avoiding future architecture dependency.
Intel and SambaNova Rackscale AI: CPU Regains Inference Control Plane
At Computex 2026, Intel unveiled rack-scale AI infrastructure combining Xeon 6+ with SambaNova SN-50 RDUs, plus a fully disaggregated inference cloud (prefill on NVIDIA Blackwell, decode on RDUs) by Vector Core Compute. This aims to reposition the CPU as the central orchestrator for inference, challenging GPU dominance.
NVIDIA Locks Taiwan Supply Chain with AI Factory Stack, Vera Rubin Production Tied to Proprietary Software
NVIDIA partners with TSMC, Foxconn, and others to embed its proprietary AI software (cuLitho, Omniverse, Isaac) into semiconductor manufacturing and server assembly, while ramping Vera Rubin NVL72 production. The move uses efficiency gains (e.g., 20-50% cycle time reduction) as bait to lock the supply chain into a full-stack ecosystem, increasing switching costs for partners.
Intel Reclaims AI Control Plane: Xeon 6+ and E835 Target Agentic Orchestration
Intel launches Xeon 6+ (288 E-cores on 18A), E835 200GbE controllers, and Crescent Island GPU. The strategy repositions the CPU as the control plane for agentic AI orchestration and data movement, while using E835 Ethernet to standardize AI data center networking.
AMD Ryzen AI Halo & Max PRO 400: Local 300B Parameter Inference, but Hidden Lock-in and Thermal Limits
AMD launches Ryzen AI Halo developer platform (128GB unified memory, 200B parameter models) and Ryzen AI Max PRO 400 series (first x86 client to run 300B parameter models locally). Unified memory, ROCm optimization, and OEM partnerships aim to shift agentic AI from cloud to local, but shared memory bandwidth and thermal constraints limit real-world throughput.
AMD Backs SPEC CPU 2026 Benchmark, Emphasizing Open, Trusted Performance Measurement
AMD published a blog endorsing the upcoming SPEC CPU 2026 industry benchmark, emphasizing the critical role of open, reproducible CPU performance standards for customer infrastructure decisions in the AI era. The new benchmark updates its application suite and strengthens support for bare-metal cloud environments and parallel computing.
AMD and OpenAI Contribute MRC Protocol to OCP for Scalable AI Networking
AMD, in collaboration with OpenAI, Microsoft, and others, contributed the MRC (Multipath Reliable Connection) protocol, designed for large-scale AI training, to the Open Compute Project (OCP). AMD co-authored the specification and has already deployed MRC on its programmable Pensando DPU/NIC products, positioning its networking technology as a key enabler for resilient and adaptive AI infrastructure.
AMD and OpenAI Introduce MRC, a Next-Gen Transport Protocol for AI Training
AMD, in collaboration with OpenAI, Microsoft, and other industry leaders, has released the specification for the Multipath Reliable Connection (MRC) protocol. MRC addresses performance bottlenecks of RoCEv2 in hyperscale AI training clusters through intelligent packet spraying, selective retransmission, and network-signaled congestion control, aiming to improve bandwidth utilization and job resilience.
Seven European Tech Giants Issue Joint Call for EU Reform to Safeguard Tech Sovereignty
CEOs of seven leading European tech companies, including ASML, Airbus, Ericsson, and Mistral AI, co-signed an open letter urging the EU to simplify digital regulations and reform competition policy. This aims to accelerate the scaling of next-gen technologies like industrial AI in Europe to enhance global competitiveness.
AMD Showcases Heterogeneous Computing Strategy for Enterprise AI with Dell
At Dell Technologies World, AMD highlighted its heterogeneous computing portfolio, aiming to match the right compute engine to specific enterprise AI workloads, while emphasizing hardware-based security and manageability. This signals a shift in AI infrastructure from generic solutions to fine-tuned, scenario-specific deployments.
AMD Proposes New AI Infrastructure Networking Paradigm: From Lossless Fabrics to Intelligent Endpoints
AMD published a blog outlining seven key questions for building large-scale AI infrastructure, arguing that traditional lossless Ethernet or InfiniBand architectures face cost and complexity bottlenecks. It advocates shifting network intelligence and reliability functions from expensive, specialized switches to intelligent NICs, enabling reliable transport over standard (potentially lossy) Ethernet to reduce TCO and simplify operations.
AMD and Liquid AI Discuss Efficient AI Architecture from Silicon to Systems
AMD's CTO and Liquid AI's CEO discuss the evolution of AI architecture, emphasizing efficiency as key to extending AI from the cloud to edge and endpoint devices. They argue that co-design from silicon to systems enables low-power, responsive AI inference, supporting always-on agents and multi-model orchestration.
AMD Extends Edge AI Architecture to Space, Defining Orbital Computing Paradigm
AMD's CTO proposes applying the core principles of 'performance-per-watt' and 'mission-critical reliability' from terrestrial edge AI to space computing. The company is providing a repeatable platform foundation for in-orbit satellite intelligence and future orbital data centers through heterogeneous computing, open software stacks, and modular system design.
AMD Highlights AI PC as Critical Infrastructure for Enterprise Agentic AI in IDC White Paper
AMD released an IDC white paper indicating that over 80% of enterprises are planning, piloting, or deploying AI PCs to support scaled Agentic AI. The report highlights high-performance NPUs and on-device AI processing as critical for enabling real-time, secure workflows, signaling a shift in enterprise AI infrastructure from cloud to endpoint.
Arm Partners with Monash University Malaysia to Advance Semiconductor Talent for AI Era
Arm announced a collaboration with Monash University Malaysia's School of Engineering, donating IC design development boards and appointing an executive as a guest lecturer. The initiative aims to cultivate semiconductor talent with hands-on Arm architecture and modern system design experience for the AI era.
Microsoft Partners with Domestic Operators to Build Sovereign AI Infrastructure in Japan
Microsoft announced a $10B investment in Japan over four years, with a key pillar being a collaboration with Sakura Internet and SoftBank. This partnership will offer GPU-based AI compute services through Azure, managed by domestic providers to ensure data residency within Japan. This addresses the demand for sovereign AI infrastructure for sensitive workloads.
AMD Announces Breakthrough MLPerf Inference 6.0 Results, Showcasing Multinode Scaling and Multimodal Capabilities
AMD's MLPerf Inference 6.0 submission, powered by Instinct MI355X GPUs, surpassed 1 million tokens per second for the first time on models like Llama 2 70B and GPT-OSS-120B. The results highlight efficient multinode scaling, rapid enablement of new workloads (e.g., text-to-video model Wan-2.2-t2v), and reproducible performance across a broad partner ecosystem.
Arm Partners with Malaysian University to Cultivate Semiconductor Talent for AI Era
Arm announced a collaboration with Monash University Malaysia's School of Engineering, donating IC design development boards and establishing a guest lecturer program. The initiative aims to provide students with hands-on experience in AI chip design based on Arm architecture, addressing the growing demand for advanced computing talent in the APAC region.