MediaTek Advances CoWoS, EMIB-T and 3.5D Packaging Strategy

MediaTek is expanding its advanced packaging and interconnect capabilities as it prepares to scale a new generation of custom AI accelerator ASICs for hyperscale data centers. During its second-quarter earnings call, the company outlined an increasingly system-level strategy built around large-die ASIC design, CoWoS and EMIB-T packaging, 3.5D integration, HBM, chip-to-chip connectivity, 448G SerDes, co-packaged copper and co-packaged optics. MediaTek said its first AI accelerator ASIC will enter production in the fourth quarter of 2026, supporting data center revenue expected to exceed US$2 billion this year, while a larger and more powerful second-generation device remains on schedule for initial production in early 2028. CEO Rick Tsai confirmed that progress with EMIB-T has become more constructive, including improving yields and technology maturity for volume production. MediaTek is also maintaining capabilities across multiple packaging technologies, including TSMC CoWoS. The company is positioning this packaging expertise within an end-to-end 3.5D platform that combines its own die-to-die IP, memory interfaces, I/O, packaging technology and validated design flows. MediaTek said its 2nm-based 448G SerDes is on schedule and is expected to become available during the second half of 2027. The electrical interface is being developed alongside a Co-Package Copper (CPC) system solution. Beyond 448G electrical signaling, MediaTek expects future generations to move increasingly toward optical connectivity using TSMC's COUPE platform. MediaTek raised its targeted share of the 2027 AI accelerator market to 15%-20%, up from 10%-15%. The board approved a discretionary US$5 billion financing framework for capacity and strategic expansion.