MediaTek 2026-08-04
Vendor Strategy Impact: Major Conf: 85%

MediaTek Adopts Dual Packaging: CoWoS and Intel EMIB-T for ASIC

Summary

MediaTek CEO confirms ASIC projects adopt Intel EMIB-T packaging alongside TSMC CoWoS. EMIB-T uses micro bridges for high-density interconnects, supporting HBM, achieving 8-10x reticle area at lower cost. Dual-track strategy highlights packaging as a key competitive dimension in AI chips.

Key Takeaways

MediaTek CEO Cai Lixing confirmed for the first time that the company's ASIC projects have adopted Intel's EMIB-T advanced packaging technology. MediaTek, as a key partner for data center clients, leverages deep design optimization with TSMC and collaboration with major packaging vendors to develop large-die high-performance ASICs based on both CoWoS and EMIB-T paths. Intel's EMIB is a 2.5D packaging solution that uses micro bridges and multi-layer routing to replace large silicon interposers, supporting HBM integration. The EMIB-T version adds TSV technology for easier design migration. EMIB is expected to achieve composite areas of eight to ten times the reticle size this year, offering high-density compute at lower cost. MediaTek's dual-track approach underscores that packaging has become a core competitive dimension in the AI chip landscape.

Why It Matters

MediaTek's dual-track packaging appears flexible but is fundamentally a defensive move against TSMC dependency and a hedge to lock clients into its design ecosystem. Hidden risks include immature yield and reliability of Intel's EMIB-T for very large dies, and added design complexity. Signal integrity issues may arise with micro-bridge interconnects at high bandwidths compared to TSMC's direct silicon interposer, potentially increasing latency and power. Thermal management remains a critical bottleneck for 2.5D packages, unaddressed in the announcement. Clients face dual-track lock-in: adapting to MediaTek's specific packaging middleware raises switching costs.

PRO Decision

【Vendors】Competing ASIC designers like Broadcom and Marvell should highlight the maturity and stability of single-vendor packaging (e.g., TSMC CoWoS), attacking the unknown risks of Intel EMIB-T. They can offer reference designs directly supporting one path to reduce client lock-in.
【Enterprises】CIOs and architects should demand detailed performance comparisons, cost breakdowns, and migration paths for both packaging options. Require independent benchmarks for power, latency, and thermal performance under AI workloads. Avoid being locked into MediaTek's specific packaging middleware; maintain design portability by engaging multiple packaging vendors directly.
【Investors】Look beyond the PR spin: MediaTek's dual-track is a defensive response to TSMC capacity constraints and Intel subsidies. Monitor whether MediaTek can maintain profit margins across both paths and the yield ramp risks of EMIB-T. Long-term, packaging diversification may reduce TSMC's pricing power but increase MediaTek's design costs, potentially eroding margins.

Source: 快科技
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