Reports
AI-generated structured vendor updates
OpenAI and Broadcom launch Jalapeño inference ASIC: 9-month tapeout, 2027 mass production, targets GPU replacement
OpenAI and Broadcom unveil Jalapeño, a custom inference ASIC designed in 9 months using OpenAI's own LLMs. Early benchmarks show superior performance-per-watt vs. current GPUs. Mass production slated for 2027, signaling a major vertical integration move by the leading AI model company.
Samsung Re-accelerates 1.4nm Node R&D, Adopts High-NA EUV Lithography
Samsung Electronics is re-accelerating its 1.4nm (SF1.4) process node R&D, targeting mass production by 2028-2029. It has procured High-NA EUV lithography equipment from ASML for its NRD-K R&D complex and ordered tools for 12th-gen V-NAND with wafer stacking. The move aims to catch up with TSMC and Intel in the AI chip foundry race.
TSMC, ASML, imec Demonstrate 300mm 2D Material CMOS with 50nm CPP, 94% Yield
TSMC, ASML, and imec jointly demonstrated the first 300mm wafer-scale integration of 2D material transistors at VLSI 2026, achieving 50nm contacted poly pitch (CPP) for MoS₂ nFET and WS₂/WSe₂ pFET with 28nm channel length and 94% yield, marking a critical step toward industrializing 2D semiconductors.
Google Caps Meta's Gemini Access: AI Compute Bottleneck Reshapes Cloud Ecosystem
Google restricts Meta's access to Gemini API due to compute capacity shortage, delaying Meta's AI projects. This reveals that even with custom TPUs and massive data centers, Google cannot meet surging demand, forcing the industry to reassess AI compute allocation and supply chain resilience.
TSMC Adds Winbond to WoW 3D Stacking Memory Supply, Breaking DRAM Oligopoly
Winbond joins TSMC's Wafer-on-Wafer (WoW) 3D stacking advanced packaging supply chain, becoming a new DRAM wafer supplier alongside Samsung, SK Hynix, and Micron. This move reduces reliance on the three global DRAM giants and strengthens AI chip packaging supply resilience. Winbond provides DRAM wafers for vertical stacking with TSMC logic wafers, offering 8GB capacity and 256GB/s bandwidth via its CUBE solution.
NVIDIA Space-1 targets orbital AI compute, locking ecosystem with Vera Rubin
NVIDIA hires chief software architect for Space-1, its orbital AI computing system powered by Vera Rubin chips. The system must withstand radiation and temperature extremes. This signals a shift from concept to engineering, though commercial viability remains distant.
Jia Yangqing exits NVIDIA as DGX Lepton shutdown reveals software layer failure
Jia Yangqing leaves NVIDIA after DGX Lepton underperforms and open-source commitments are broken. NVIDIA acquired Lepton AI for ~$700M, rebranded as DGX Cloud Lepton, but service ceased mid-2025. The event signals NVIDIA's failed software layer expansion, shifting control back to hyperscalers.
Samsung and SK Hynix Announce $300B Investment to Dominate AI Memory and Foundry
Samsung and SK Hynix announce a 10-year, 1,000 trillion won investment plan to expand HBM4 production, improve 3nm GAA yield, and build new AI chip fabs. This aims to cement their HBM duopoly and close the gap with TSMC in advanced foundry, reshaping global AI infrastructure supply chain costs.
OpenAI and Broadcom Tape Out First Inference ASIC Jalapeño in 9 Months, Targeting NVIDIA Dominance
OpenAI and Broadcom unveil Jalapeño, their first custom inference ASIC, fabricated on TSMC 3nm and optimized for Transformer models. Targeting a 50% inference cost reduction, it taped out in 9 months and is slated for deployment in gigawatt-scale data centers by late 2026, marking OpenAI's strategic pivot to full-stack AI infrastructure and a direct challenge to NVIDIA's inference hegemony.
Qualcomm Acquires Modular for $3.9B, Open-Sources Mojo to Break CUDA Lock-In
Qualcomm acquires Modular for $3.9B in stock and open-sources Mojo, a Python-compatible systems language. Mojo targets CUDA dependency, aiming to provide a high-performance alternative for AI developers. This move strengthens Qualcomm's AI inference chip software stack and edge AI competitiveness.
NVIDIA Rubin Mandates 100% Liquid Cooling with 45°C Warm Water, Reshaping Data Center Thermal Design
NVIDIA reveals Rubin platform's full liquid cooling design: 100% liquid, 45°C warm water inlet, eliminating chillers and fans. Mass production starts H2 2026, with a mandate for all data centers to transition to liquid cooling, marking a definitive shift in AI thermal management.
Microsoft Cuts Azure China R&D: Geopolitics Forces AI Cloud Retreat
Microsoft is cutting 200-400 Azure R&D roles in Beijing and Shanghai, with departures by July 2026. US AI chip export controls and China's data security laws make frontier AI development impossible. Azure China, operated via 21Vianet, has <5% market share vs Alibaba (30%) and Huawei (19%).
Qualcomm Enters AI Datacenter with Dragonfly ARM CPU, Meta Signs Multi-Generation Deal
Qualcomm unveils Dragonfly C1000 ARM-based datacenter CPU, AI300 accelerator, and interconnect. Meta commits to multi-generation CPU supply, Microsoft Azure to deploy HBC chips. Qualcomm targets $15B+ datacenter revenue by FY2029, acquires Modular for software stack.
OpenAI and Broadcom unveil Jalapeño inference ASIC to bypass NVIDIA GPU dependency
OpenAI and Broadcom launch Jalapeño, a custom ASIC for LLM inference, achieving tape-out in 9 months. OpenAI designs architecture, Broadcom provides networking, Celestica handles integration. Planned for large-scale deployment by end-2026 with gigawatt-scale datacenters, aiming to cut inference costs and reduce NVIDIA dependency.
NVIDIA Unveils Vera CPU for AI Agents, Shifting Control from x86 to Proprietary Silicon
At the annual meeting, Huang announced Vera CPU for AI agents paired with Rubin GPU, claimed Blackwell delivers 30x token throughput over next-best platform, and reiterated CUDA as a moat. This move aims to shift AI compute control from general-purpose CPUs to NVIDIA's proprietary architecture.
TSMC Bets on CoPoS and Glass Substrates: Packaging Paradigm Shifts from Wafer-Level to Panel-Level, AI Chip TCO Inflection
TSMC is replacing CoWoS with CoPoS (panel-level packaging), using 750x620mm square panels and glass core substrates, achieving 20-30% unit area cost reduction. Volume production targets 2028, with AMD Zen 7 as first key customer. This fundamentally alters AI chip packaging economics and capacity scaling.
MediaTek Lands Exclusive Google TPU v9 Inference Upgrade Triggerfish with 2x SRAM
Google plans a TPU v9 inference upgrade, Triggerfish, exclusively fabbed by MediaTek. It features 2-3x on-chip SRAM, HBM4E DRAM, and a simulation die for local management. Production starts late 2027 with 1-2M units lifecycle, unit price ~30% higher than Humufish.
Google TPU v9 Switches to MediaTek, Breaking Broadcom's AI ASIC Monopoly
Google moves its TPU v9 Humufish design and integration contract from Broadcom to MediaTek, which handles I/O chip design and packaging. Combined with a split-foundry strategy (TSMC N2 compute, Samsung 2nm I/O), this marks a systematic effort to build a multi-vendor, multi-node supply chain, directly dismantling Broadcom's dominance in custom AI ASICs.
Intel AI Box Ultra Hits the Road: PC-class Compute Enters Car, Locks Down Edge AI Ecosystem
Intel and Changan Auto launch the AI Box Ultra solution based on the Core Ultra platform, bringing PC-class compute and Android app ecosystem to the cockpit. It emphasizes on-device AI inference, privacy, and offline capability. The move targets Qualcomm and NVIDIA but hides X86 power/thermal drawbacks.
Intel at Computex 2026: CPU as Agentic AI Orchestrator, x86 Reclaims Inference Control
At Computex 2026, Intel unveiled the 288-core Xeon 6+ (Intel 18A) and 3rd-gen Core Ultra, claiming Agentic AI shifts CPU:GPU ratio from 1:8 to 1:1. Partnering with SambaNova and Foxconn for rack-scale inference systems, Intel repositions the CPU as the orchestrator for multi-step AI reasoning, aiming to reclaim control from GPU-centric architectures.