Google TPU v9 Switches to MediaTek, Breaking Broadcom's AI ASIC Monopoly
Summary
Key Takeaways
Confirmed by multiple supply chain sources, Google has assigned the design and integration of its TPU v9 revision, codenamed Humufish, exclusively to MediaTek. The chip, slated for 2028 production, includes 4 TSMC N2 (2nm) compute dies, 3 I/O dies, and 12 HBM4e stacks, serving as the core AI compute platform for Google's 2028-2029 datacenters. MediaTek handles I/O chip design, wafer procurement, and backend packaging, while the compute die remains Google-designed. This marks a definitive shift from Broadcom to MediaTek for the TPU v9 project. MediaTek's datacenter ASIC revenue share is projected to reach 59% by 2028, up from 36% in 2027. Concurrently, Google's next-gen TPU Icefish adopts a split-foundry strategy: TSMC produces the compute die on 1.4nm, Samsung fabricates the memory I/O die on 2nm, with MediaTek co-designing the overall architecture. Google is systematically reducing reliance on Broadcom, building a flexible supply chain spanning TSMC, Samsung, Intel, and multiple design partners.
Why It Matters
Google's move is fundamentally a defensive play to break Broadcom's lock-in on custom AI ASICs. Broadcom previously controlled the entire Die-to-Die interconnect (BoW, UCIe) and packaging integration (CoWoS) for TPU v9, tying Google's memory bandwidth and chip-to-chip latency to Broadcom's proprietary SerDes IP and HBM memory controllers. By switching to MediaTek and adopting a split-foundry model, Google severs this binding. However, the report hides critical risks: MediaTek lacks proven experience in hyperscale datacenter interconnects. Its 112G/224G PAM4 SerDes performance under long-reach transmission (BER, power efficiency) is unvalidated at scale. Furthermore, the cross-foundry strategy (TSMC N2 + Samsung 2nm) introduces thermal-mechanical stress and signal integrity issues at the die-to-die interface, potentially creating tail latency bottlenecks for HBM4e memory access, directly degrading large model training throughput.
PRO Decision
【Vendors】 Broadcom must immediately double down on integrated networking+compute ASIC value propositions for other hyperscalers (Microsoft, Meta), emphasizing its SerDes IP and HBM controller socket compatibility across nodes. Accelerate Co-Packaged Optics (Tomahawk 6, Jericho 3) to bypass electrical interconnect bottlenecks and re-monopolize die-to-die bandwidth. 【Enterprises】 CIOs and architects should flag supply chain fragmentation risk. Split-foundry and cross-fab packaging introduce yield uncertainty and product cycle delays. For those reliant on Google Cloud TPUs, prepare NVIDIA H100/B200 or AMD MI300 as compute alternatives and demand API compatibility guarantees across TPU generations to prevent model migration cost spikes. 【Investors】 This marks Broadcom's moat erosion in custom ASICs. Google's shift to MediaTek is a bellwether for hyperscaler de-Broadcomization. Reduce Broadcom positions, increase MediaTek holdings, and monitor TSMC and Samsung CoWoS/I-Cube capacity allocation. Intel's IFS winning Google's Icefish memory I/O would be a pivotal moment.
Get 3-5 key AI infrastructure signals weekly →
💬 Comments (0)