Samsung Electronics
2026-06-30
Samsung Re-accelerates 1.4nm Node R&D, Adopts High-NA EUV Lithography
Summary
Key Takeaways
Samsung Electronics is re-accelerating its 1.4nm (SF1.4) process node R&D, previously delayed from 2027 to 2029 due to a shift in foundry business priorities. Samsung has shared its SF1.4 process blueprint with major equipment vendors like Applied Materials and Lam Research, aiming to co-develop customized tool sets.
The company has procured High-NA EUV lithography systems (0.55 NA) from ASML, installed at the NRD-K R&D complex. High-NA EUV is expected to be first used in production at SF1.4, reducing multi-patterning steps and improving resolution.
Samsung also ordered equipment for 12th-gen V-NAND, targeting mass production around 2030 with a wafer stacking architecture. The foundry plans to achieve volume production of SF1.4 by 2028-2029, aiming to catch up with TSMC and Intel in the race for advanced AI chip manufacturing.
Why It Matters
Samsung's re-acceleration of SF1.4 with High-NA EUV is a defensive move against TSMC and Intel. TSMC's N2 (GAA) and A14 (1.4nm) are on track, while Intel's 18A targets 2025. Samsung aims to leverage High-NA EUV for single-patterning at 1.4nm to reduce multi-patterning complexity and tail latency risks, but hides the extreme cost (>$400M per tool) and unresolved engineering challenges (resist sensitivity, mask defects). The repeated delay from 2027 to 2029 signals poor yield ramp capability. AI chip designers face uncontrollable process cadence and high switching costs if locked into Samsung's foundry. V-NAND wafer stacking also introduces thermal management and signal integrity bottlenecks.
PRO Decision
【Vendors (TSMC, Intel)】Exploit Samsung's SF1.4 delay to 2029 by accelerating customer adoption of N2/A14 and 18A nodes. Emphasize proven yield, mature GAA ecosystem, and PowerVia backside power delivery. Secure High-NA EUV supply priority with ASML to constrain Samsung's capacity.
【Enterprises (AI chip designers)】Conduct multi-sourcing foundry audits immediately. Demand SF1.4 PDK maturity, defect density data, and PPA benchmarks from Samsung. Maintain backup designs with TSMC/Intel to mitigate process cadence risks. For V-NAND, validate thermal management and read/write latency under AI workloads.
【Investors】Watch for CapEx overrun risk: High-NA EUV purchases will increase depreciation, but delayed production may prolong ROI. Compare Samsung's repeated delays with TSMC/Intel's clear roadmaps. Monitor customer churn and capacity utilization; if key clients (e.g., NVIDIA) defect, Samsung's advanced-node investment becomes stranded cost.
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