Reports
AI-generated structured vendor updates
TSMC targets 100,000 monthly 2nm wafers by 2026, fueled by AI demand
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英伟达AMD博通追单：台积电3nm月产18万片目标有望提前至Q4初达成，2nm年底冲刺10万片
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TSMC Accelerates 1.4nm Production, Develops EMIB-like Packaging to Rival Intel
TSMC accelerates its 1.4nm (A14) process to trial production in Q3 2027, using second-gen GAA nanosheet transistors with 20-23% density improvement. It also develops an EMIB-like advanced packaging to counter Intel's EMIB-T, aiming to retain AI chip packaging business.
TSMC Accelerates 1.4nm Process, Partners with Unimicron on EMIB-Like Packaging to Counter Intel
TSMC accelerates its 1.4nm (A14) process to mid-2028 mass production, using second-gen GAA NanoFlex Pro transistors and existing EUV lithography. It also partners with Unimicron on EMIB-like packaging to alleviate CoWoS capacity constraints and prevent AI chip customer loss to Intel's packaging platform.
Samsung locks 60% capacity in long-term deals, HBM4E sampling, memory shortage through 2028
Samsung Q2 2026 operating profit surged 1814% to 89.5 trillion won, driven by AI memory demand. HBM4E samples delivered, HBM4 revenue to triple QoQ. Samsung locks 60-70% capacity in 5-year LTAs, warns memory shortage through 2028, worsening in 2027.
TSMC 2nm Volume Production Begins, AMD First to Launch Venice and MI455X
TSMC has fully ramped its 2nm process at five fabs, contributing ~3% of wafer revenue in Q2. AMD launches the first 2nm-based products: EPYC Venice (256 cores) and Instinct MI455X (320B transistors, 432GB HBM4), shipping in Q3. Samsung targets 1.4nm by 2029, Intel 18A introduces High-NA EUV, intensifying foundry competition.
Samsung Re-accelerates 1.4nm Node R&D, Adopts High-NA EUV Lithography
Samsung Electronics is re-accelerating its 1.4nm (SF1.4) process node R&D, targeting mass production by 2028-2029. It has procured High-NA EUV lithography equipment from ASML for its NRD-K R&D complex and ordered tools for 12th-gen V-NAND with wafer stacking. The move aims to catch up with TSMC and Intel in the AI chip foundry race.
Huawei's LogicFolding: 3D Stacking Rewrites AI Chip Rules
Huawei's Tau Scaling Law and LogicFolding architecture boost transistor density by 55% and power efficiency by 41% via vertical logic stacking, targeting 1.4nm-class by 2031. Ascend 920/910C chips are now used for DeepSeek V4-Pro post-training, signaling real-world AI workload deployment and challenging Nvidia's dominance in China.
Huawei's Tao Law: LogicFolding Bypasses Lithography, 55% Density Gain on Fixed Node
At ISCAS 2026, Huawei's He Tingbo unveiled the Tao Law, replacing geometric scaling with temporal optimization targeting tau (characteristic time). LogicFolding vertically stacks active layers to shorten critical paths, achieving 55% transistor density increase and 41% energy efficiency gain on a fixed node. Kirin 2026 reaches 3.1GHz; Ascend series will adopt LogicFolding. The roadmap projects equivalent 1.4nm density by 2031, fundamentally challenging Moore's Law's lithography dependency.
NVIDIA and SK hynix Co-Architect Next-Gen Memory for AI Factories, Locking HBM4 to Vera Rubin
NVIDIA and SK hynix announce a multi-year tech partnership to co-develop next-gen memory for Vera Rubin, RTX Spark, and Jetson Thor. Separately, SK Telecom deploys a gigawatt-scale AI cloud using the full DGX stack, targeting 2027. This elevates SK hynix from supplier to co-architect, strengthening NVIDIA's lock-in on HBM and the AI ecosystem.