Reports
AI-generated structured vendor updates
Samsung Re-accelerates 1.4nm Node R&D, Adopts High-NA EUV Lithography
Samsung Electronics is re-accelerating its 1.4nm (SF1.4) process node R&D, targeting mass production by 2028-2029. It has procured High-NA EUV lithography equipment from ASML for its NRD-K R&D complex and ordered tools for 12th-gen V-NAND with wafer stacking. The move aims to catch up with TSMC and Intel in the AI chip foundry race.
Huawei's LogicFolding: 3D Stacking Rewrites AI Chip Rules
Huawei's Tau Scaling Law and LogicFolding architecture boost transistor density by 55% and power efficiency by 41% via vertical logic stacking, targeting 1.4nm-class by 2031. Ascend 920/910C chips are now used for DeepSeek V4-Pro post-training, signaling real-world AI workload deployment and challenging Nvidia's dominance in China.
Huawei's Tao Law: LogicFolding Bypasses Lithography, 55% Density Gain on Fixed Node
At ISCAS 2026, Huawei's He Tingbo unveiled the Tao Law, replacing geometric scaling with temporal optimization targeting tau (characteristic time). LogicFolding vertically stacks active layers to shorten critical paths, achieving 55% transistor density increase and 41% energy efficiency gain on a fixed node. Kirin 2026 reaches 3.1GHz; Ascend series will adopt LogicFolding. The roadmap projects equivalent 1.4nm density by 2031, fundamentally challenging Moore's Law's lithography dependency.
NVIDIA and SK hynix Co-Architect Next-Gen Memory for AI Factories, Locking HBM4 to Vera Rubin
NVIDIA and SK hynix announce a multi-year tech partnership to co-develop next-gen memory for Vera Rubin, RTX Spark, and Jetson Thor. Separately, SK Telecom deploys a gigawatt-scale AI cloud using the full DGX stack, targeting 2027. This elevates SK hynix from supplier to co-architect, strengthening NVIDIA's lock-in on HBM and the AI ecosystem.