Reports
AI-generated structured vendor updates
TSMC Develops EMIB-Like Packaging with Kinsus to Counter Intel's CoWoS Threat
TSMC, in response to CoWoS capacity constraints and potential customer loss, is developing an EMIB-like advanced packaging technology with Kinsus, aiming to simplify manufacturing steps and reduce costs, preventing clients from shifting to Intel's packaging platform, highlighting the strategic importance of advanced packaging in AI chip competition.
MediaTek ra mắt chip mới, hứa hẹn giải quyết khủng hoảng silicon toàn cầu
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TSMC Develops EMIB-like Packaging to Challenge Intel and Ease CoWoS Bottleneck
TSMC is developing an EMIB-like advanced packaging technology that uses small silicon bridges instead of large silicon interposers, reducing cost and complexity while easing CoWoS capacity constraints. This move counters Intel's EMIB technology and addresses the growing packaging demands of AI accelerators, securing TSMC's dominance in advanced packaging.
台积电亚利桑那二厂主体建筑完成Q4进入设备装机阶段
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苹果M7芯片跳过M6代际直指端侧AI推理加速
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高通通知客户9月1日后骁龙芯片涨价两位数
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ASML Q2营收93亿欧元 High-NA EUV在Intel 18A达到生产级良率
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NVIDIA Prepay $1.5B to Amkor for US 2nm/3nm/HBM4 Advanced Packaging
NVIDIA prepays $1.5B to Amkor to expand advanced packaging capacity in Arizona, covering 2nm/3nm/HBM4. This onshores AI chip packaging, complementing Wistron's system integration, to reduce reliance on Taiwan and secure supply for Vera Rubin and Blackwell Ultra.
Intel Accelerates 14A to 2027H2 Risk Production, 18A Yield Exceeds Target by 25%, Capex Raised to $20B
Intel announced 14A process acceleration to risk production in 2027H2 with HVM in 2028, 18A yield exceeding target by 25% supporting Panther Lake volume, and raising 2026 capex to $20B, signaling an aggressive foundry push. Advanced packaging EMIB-T becomes a profit pillar.
Microsoft Azure Deploys AMD Helios Rack with MI455X GPUs, Launches Three New VM Families
Microsoft Azure announces the deployment of AMD Helios rack-scale AI platform, featuring 72 Instinct MI455X GPUs, 31TB HBM4 memory, and 1.4PB/s bandwidth per rack. Three new VM families target AI inference, data engineering, and HPC, powered by 6th-gen EPYC Venice CPUs and Pensando DPUs.
ASML Q2营收93.3亿欧元超预期，上调全年指引
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Intel与Fortinet战略合作开发SP6安全处理器，18A工艺良率提升至85%
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NVIDIA公开Rubin GPU架构细节：3360亿晶体管，智能体AI性能较Blackwell提升10倍
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TSMC Pledges $100B More for 6 US Fabs, Localizing 3nm for AI Chip Supply Chain
TSMC announces an additional $100B investment in Arizona, bringing total US commitment to $265B, with plans for 6 fabs focused on 3nm and beyond. This move localizes advanced process for AI chip demand from NVIDIA, Apple, AMD, reshaping global semiconductor supply chain. Q2 net profit surged 77% YoY, FY capex raised to $60-64B.
IBM Unveils 0.7nm Nanostack 3D Transistor, Doubling Density and Extending Moore’s Law
IBM debuts the world’s first sub-1nm chip technology at 0.7nm node using a nanostack 3D transistor architecture, packing nearly 100 billion transistors with double the density of its 2nm node. It delivers 50% performance gain or 70% energy efficiency improvement, and 40% SRAM scaling for AI workloads.
Intel 18A Yield Hits 85%, Secures Orders from NVIDIA, OpenAI, Reshaping Foundry Landscape
Intel reports 18A process yield improvement to 85%, from 65% last quarter, nearing TSMC N2's 90%. Secured foundry deals with NVIDIA, AMD, OpenAI, etc. EMIB advanced packaging yield reaches 98%, used in NVIDIA Feynman, Google TPU. This marks a strategic inflection in AI chip manufacturing.
Meta Invests $9.17B in Canada AI Data Center, Iris AI Chip Mass Production Begins MTIA Roadmap
Meta announced a $9.17B AI data center in Canada with 1GW capacity, and its first in-house AI chip Iris will mass produce in September, kicking off the MTIA four-generation roadmap. Meta targets 14GW compute by 2027, using 6-month chip iterations to challenge NVIDIA's annual cadence and reduce GPU dependency.
AWS Sells Trainium 3 Externally, Challenging NVIDIA's AI Training Chip Dominance
AWS begins external sales of its Trainium 3 AI training chip, fabricated on TSMC 3nm process, delivering 2.52 PFLOPS per chip. Early customers include Anthropic and Uber. This move directly challenges NVIDIA's dominance and marks AWS's strategic shift from cloud provider to chip vendor.
TSMC Ramps PIC Capacity to 25K Wafers, CPO Silicon Photonics Poised to Disrupt AI Interconnects
TSMC plans to expand its PIC capacity to 25,000 wafers per month by 2028, with its COUPE platform becoming critical for reducing latency and power in AI systems. Initial capacity is allocated to NVIDIA, Broadcom, and AMD, marking CPO's transition from lab to mass production and accelerating the shift from electrical to optical AI interconnects.
NVIDIA Rigel Core: Single-Threaded CPU as the New Control Plane for Agentic AI
NVIDIA unveils Rosa CPU architecture with custom Rigel core (Arm v9.2), targeting single-threaded performance for Agentic AI workloads, paired with Feynman GPU (1.6nm, 50 PFLOPS) in 2028. This shifts CPU design from core-count scaling to serial-latency optimization, directly challenging AMD EPYC and Intel Xeon dominance.