Reports
AI-generated structured vendor updates
Huawei's LogicFolding: 3D Stacking Rewrites AI Chip Rules
Huawei's Tau Scaling Law and LogicFolding architecture boost transistor density by 55% and power efficiency by 41% via vertical logic stacking, targeting 1.4nm-class by 2031. Ascend 920/910C chips are now used for DeepSeek V4-Pro post-training, signaling real-world AI workload deployment and challenging Nvidia's dominance in China.
NVIDIA and Coherent Scale 6-Inch InP Fab, Optical Interconnect Becomes AI Infrastructure's New Bottleneck Breaker
NVIDIA invests $2B and commits multi-billion purchases to Coherent's expanded 6-inch indium phosphide fab in Texas, scaling production of lasers and optical modules for AI interconnects. This addresses copper's distance and power limitations in large GPU clusters (e.g., Vera Rubin Ultra NVL576), pushing co-packaged optics into volume manufacturing.
Qualcomm's RISC-V Gamble: Tenstorrent Acquisition and Edge AI Pivot
Qualcomm pivots from ARM to open-source RISC-V, acquiring Ventana Micro and targeting Tenstorrent for $8-10B. Launches 'Dragonfly' brand for custom AI accelerators, aiming for $35B data-center revenue by 2031, betting on edge AI and AI agents.
AMD MLPerf 6.0: MI350 GPUs Achieve 3.5x Leap with MXFP4, Debut Multi-Node Training
AMD submitted its most comprehensive MLPerf Training 6.0 results, including first multi-node training (FLUX.1 on 512 GPUs) and MXFP4 training recipe. MI355X delivers 3.5x generational leap over MI300X on Llama 2-70B, within 5% of NVIDIA B200. 10 ecosystem partners validated reproducibility.
HBM Bottleneck Reshapes AI Infrastructure: Asian Memory Makers Gain Leverage Over Nvidia
SK Hynix, Samsung, and Micron have crossed $1 trillion market cap as HBM becomes the hard limit in AI infrastructure. Asian suppliers now account for 90% of Nvidia's production costs, shifting the bottleneck from GPU compute to stacked memory and advanced packaging.
AMD and Rackspace Deploy 30MW Governed AI Stack: Ecosystem Restructuring from Silicon to Outcomes
AMD and Rackspace sign a definitive agreement to deploy 30MW of AMD AI compute (Instinct GPUs including MI355X, EPYC CPUs) across Rackspace's data centers, creating a governed enterprise AI stack with single accountability from silicon to outcomes, targeting regulated industries.
AMD Acquires MEXT: AI-Predicted Flash Nears DRAM Performance to Cut AI Memory TCO
AMD acquires MEXT, an AI-driven memory optimization startup. MEXT's predictive technology makes NAND Flash behave like DRAM, expanding effective memory capacity for AI workloads and lowering TCO. The tech will be integrated across AMD's data center portfolio (EPYC, Instinct) to address memory bottlenecks in large models.
AMD Open-Sources AI Software Stack on Vultr, Taking on NVIDIA CUDA Ecosystem
AMD launches a suite of open-source, modular enterprise AI software components on Vultr Marketplace, including AMD Inference Microservices (AIMs), AI Workbench, Resource Manager, and Solution Blueprints. This aims to provide production-grade AI infrastructure without vendor lock-in, directly challenging NVIDIA's CUDA ecosystem.
NVIDIA & SK hynix Deepen Memory Co-Engineering: Custom HBM for Vera Rubin and Jetson Thor
NVIDIA and SK hynix have announced a multiyear partnership to co-develop next-generation custom memory for NVIDIA's AI factory ecosystem, including Vera Rubin supercomputers, Vera CPUs, RTX Spark PCs, and Jetson Thor robotic platforms. SK hynix will also use NVIDIA CUDA-X libraries and Omniverse to accelerate semiconductor design and build fab digital twins.
AMD, Dell, Cambridge Launch UK Sovereign AI Lab to Challenge NVIDIA's CUDA Dominance with Open ROCm
AMD, Dell, and the University of Cambridge launch the Sovereign AI Innovation Lab (SAIL) in the UK, deploying Zenith supercomputer with 5th Gen EPYC and Instinct MI355X GPUs, plus the Sunrise fusion AI system. The lab promotes open, interoperable AI infrastructure based on AMD ROCm, challenging NVIDIA's CUDA lock-in and offering long-term technology choice for national AI initiatives.
AMD EPYC Challenges Rack-Scale Density for Agentic AI Control
AMD claims its EPYC processors lead in rack-scale performance for agentic AI's CPU-intensive services (orchestration, caching, databases). Under a 100kW rack model, EPYC 9965 'Turin' delivers 2.37x throughput over NVIDIA Vera, with next-gen 'Venice' projected at 3.30x. Emphasizes deployability on current x86 platforms, avoiding future architecture dependency.
Intel and SambaNova Rackscale AI: CPU Regains Inference Control Plane
At Computex 2026, Intel unveiled rack-scale AI infrastructure combining Xeon 6+ with SambaNova SN-50 RDUs, plus a fully disaggregated inference cloud (prefill on NVIDIA Blackwell, decode on RDUs) by Vector Core Compute. This aims to reposition the CPU as the central orchestrator for inference, challenging GPU dominance.
HBM Profitability Falls Below DDR5, TrendForce Warns of Multi-Fold Price Surge in 2027
TrendForce reports that HBM per-wafer revenue fell below DDR5 64GB RDIMM in Q1 2026, making HBM less profitable. Suppliers will reallocate capacity, leading to multi-fold HBM4 contract price increases in 2027. Demand from NVIDIA Rubin Ultra and AI ASICs will further tighten supply.
NVIDIA Locks Taiwan Supply Chain with AI Factory Stack, Vera Rubin Production Tied to Proprietary Software
NVIDIA partners with TSMC, Foxconn, and others to embed its proprietary AI software (cuLitho, Omniverse, Isaac) into semiconductor manufacturing and server assembly, while ramping Vera Rubin NVL72 production. The move uses efficiency gains (e.g., 20-50% cycle time reduction) as bait to lock the supply chain into a full-stack ecosystem, increasing switching costs for partners.
Intel Reclaims AI Control Plane: Xeon 6+ and E835 Target Agentic Orchestration
Intel launches Xeon 6+ (288 E-cores on 18A), E835 200GbE controllers, and Crescent Island GPU. The strategy repositions the CPU as the control plane for agentic AI orchestration and data movement, while using E835 Ethernet to standardize AI data center networking.
Micron Partners TSMC for Custom HBM4E Logic Dies, Targets 2027 Ramp with 1-gamma DRAM
Micron plans to ramp HBM4E in 2027, transitioning to 1-gamma DRAM and using TSMC for both standard and custom logic dies. This marks a shift from standardized HBM to customized solutions, positioning memory as a strategic asset for AI inference workloads.
AMD Ryzen AI Halo & Max PRO 400: Local 300B Parameter Inference, but Hidden Lock-in and Thermal Limits
AMD launches Ryzen AI Halo developer platform (128GB unified memory, 200B parameter models) and Ryzen AI Max PRO 400 series (first x86 client to run 300B parameter models locally). Unified memory, ROCm optimization, and OEM partnerships aim to shift agentic AI from cloud to local, but shared memory bandwidth and thermal constraints limit real-world throughput.
AMD Backs SPEC CPU 2026 Benchmark, Emphasizing Open, Trusted Performance Measurement
AMD published a blog endorsing the upcoming SPEC CPU 2026 industry benchmark, emphasizing the critical role of open, reproducible CPU performance standards for customer infrastructure decisions in the AI era. The new benchmark updates its application suite and strengthens support for bare-metal cloud environments and parallel computing.
AMD and OpenAI Contribute MRC Protocol to OCP for Scalable AI Networking
AMD, in collaboration with OpenAI, Microsoft, and others, contributed the MRC (Multipath Reliable Connection) protocol, designed for large-scale AI training, to the Open Compute Project (OCP). AMD co-authored the specification and has already deployed MRC on its programmable Pensando DPU/NIC products, positioning its networking technology as a key enabler for resilient and adaptive AI infrastructure.
AMD and OpenAI Introduce MRC, a Next-Gen Transport Protocol for AI Training
AMD, in collaboration with OpenAI, Microsoft, and other industry leaders, has released the specification for the Multipath Reliable Connection (MRC) protocol. MRC addresses performance bottlenecks of RoCEv2 in hyperscale AI training clusters through intelligent packet spraying, selective retransmission, and network-signaled congestion control, aiming to improve bandwidth utilization and job resilience.