HBM Profitability Falls Below DDR5, TrendForce Warns of Multi-Fold Price Surge in 2027
Summary
Key Takeaways
TrendForce's latest research reveals a critical inflection point: in Q1 2026, HBM's per-wafer revenue was overtaken by DDR5 64GB RDIMM, based on die size, yield, and per-Gb pricing. This caused HBM profitability to fall below DDR5 for the first time.
This forces the three major suppliers—Samsung, SK Hynix, and Micron—to dynamically reallocate production between HBM and conventional DRAM. By end-2027, HBM wafer input is expected to reach 30% of total DRAM wafer input, but HBM bit supply will only be 13% of total bit supply, highlighting significant die size crowding out.
On the demand side, 2026 is driven by AI ASIC capacity upgrades (96GB/192GB to 216GB/288GB per chip), while 2027 will see NVIDIA Rubin Ultra pushing per-GPU HBM to 384GB, alongside Google TPU volume growth. This supply-demand gap gives suppliers strong pricing power.
Why It Matters
This report is a pricing power play by HBM suppliers against AI chip designers like NVIDIA, Google, and AMD. By creating a deliberate capacity allocation game between HBM and DDR5, suppliers aim to extract more profit from AI infrastructure. The hidden lock-in is the large die size of HBM, which limits bit supply despite high wafer input (30% vs 13%), making it easy to sustain price hikes. Chip designers are path-dependent on HBM for performance. The concealed cost trap is the TSV and hybrid bonding yield challenges for HBM4. High prices mask the cost of advanced packaging defects, and the PAM4 interface and 1024-bit bus will add SoC test costs, all passed to end users.
PRO Decision
[Vendors] AI chip vendors like NVIDIA, AMD, and Google should immediately invest in alternative memory architectures such as CXL-attached HBM or near-memory computing to break the oligopoly of the three HBM suppliers. They must negotiate capacity guarantees and price caps in 2027 contracts.
[Enterprises] CIOs must include stress tests for HBM price surges in their AI TCO models. Recommend allocating 20-30% budget buffer for 2027 and evaluating chip designs with smaller HBM capacity and larger L2 cache to reduce HBM dependency. Demand pricing transparency and long-term lock-in commitments from chip vendors.
[Investors] Be wary of inflated margin expectations for HBM suppliers. The price surge narrative masks HBM4 yield risks from TSV and hybrid bonding. Consider shorting HBM supplier futures and going long on CXL memory pooling and near-storage computing alternatives. Note that HBM price spikes will compress AI chip gross margins, potentially triggering a correction in chip designer stocks.
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