Reports
AI-generated structured vendor updates
AMD Helios Rack Challenges NVIDIA NVLink with Open UALoE Interconnect
At Advancing AI 2026, AMD launched the Helios rack with 72 MI455X GPUs, 18 Venice EPYC CPUs, and Pensando networking, claiming 30% higher inference token/$ vs NVIDIA NVL72. It introduced UALoE open interconnect to break NVLink lock-in, partnering with Cerebras, Cisco, and major AI firms.
NVIDIA Vera Rubin Driving Performance Per Watt, Lowest Token Cost for Partners Worldwide
...
NVIDIA Vera Rubin Platform and Dynamo 1.0 Disaggregate Inference, Shift Focus to Intelligence per Dollar
NVIDIA unveils Vera Rubin platform with a 7-chip stack (Vera CPU, Rubin GPU, NVLink 6, etc.) and Dynamo 1.0 inference disaggregation. A single NVL72 rack packs 72 GPUs/36 CPUs with 1.6 PB/s bandwidth, achieving up to 7x inference performance. The new 'intelligence per dollar' metric signals a shift from training to inference cost competition.
NVIDIA BlueField DPU In-Silicon Security Shifts AI Factory Control from Software to Hardware
NVIDIA unveils DOCA security stack (Argus, Vault, Flow) on BlueField-4 DPU, enabling hardware-isolated runtime threat detection via zero-copy memory analysis, zero-trust file access, and 800 Gb/s network enforcement. This shifts security control from host OS to DPU silicon, delivering distributed full-stack protection without compromising AI throughput, but deeply ties to Vera Rubin platform, creating ecosystem lock-in.
NVIDIA Extreme Co-Design: Vera Rubin Platform Targets Agentic Inference TCO Inflection
NVIDIA unveils an extreme co-design stack for agentic systems, featuring Vera Rubin NVL72, NVLink 6, ConnectX-9, BlueField-4, and Spectrum-X. By disaggregating inference, optimizing KV cache management, and deploying low-latency fabrics, it aims to break the throughput-interactivity tradeoff, making high-context token processing economically viable.
NVIDIA Acquires Groq LPU: Inference Architecture Shift from HBM to On-Chip SRAM
NVIDIA signs ~$20B licensing deal with Groq for LPU tech, featuring 230MB on-chip SRAM at 80TB/s bandwidth. This targets Transformer inference decode, replacing HBM bottlenecks with ultra-low latency on-chip storage, potentially reshaping the AI inference chip landscape.
NVIDIA Absorbs Groq LPU: Feynman GPU to Integrate SRAM Inference Tile, Hybrid Architecture by 2028
NVIDIA secures Groq's LPU inference technology via a non-exclusive license and key hires, planning to integrate large SRAM tiles into its 2028 Feynman GPU using TSMC SoIC hybrid bonding. This enables deterministic scheduling and 80TB/s on-chip bandwidth, shifting NVIDIA from a pure GPU vendor to a hybrid inference/training platform.