NVIDIA Absorbs Groq LPU: Feynman GPU to Integrate SRAM Inference Tile, Hybrid Architecture by 2028
Summary
Key Takeaways
NVIDIA has entered a technology licensing and talent acquisition agreement with Groq, gaining access to the LPU (Language Processing Unit) architecture optimized for inference. The LPU's key differentiators are deterministic execution and on-chip SRAM as the primary weight storage: each GroqChip offers 230MB SRAM with 80TB/s bandwidth, eliminating DRAM access latency and memory controller queueing. Compile-time scheduling removes inter-kernel timing jitter, achieving near-saturation of the decode pipeline.
NVIDIA plans to integrate LPU tiles into its next-generation Feynman GPU (2028), built on TSMC 1.6nm A16 process, using SoIC hybrid bonding to stack 3D vertical cache SRAM arrays alongside compute blocks (tensor units, control logic). This mirrors AMD's X3D CPU design but targets AI inference. NVIDIA is transitioning from a pure GPU vendor to a hybrid inference/training platform.
Why It Matters
NVIDIA's move is strategically defensive: it walls off AMD's MI300 and Intel Gaudi hybrid architectures and eliminates Groq as an independent inference threat. By integrating the LPU into Feynman, NVIDIA locks users into its full-stack GPU+SRAM bundle, stripping architectural flexibility. Switching to AMD/Intel later would require a painful software stack migration (CUDA vs ROCm/OpenVINO).
Hidden physical constraints: 230MB on-chip SRAM is insufficient for modern LLMs (e.g., Llama 3 70B ~140GB weights). The deterministic advantage vanishes when weights must be fetched from HBM, reintroducing tail latency. NVIDIA's 3D stacking will boost SRAM capacity but at a cost trap: SoIC hybrid bonding and 1.6nm process dramatically increase die cost, with undisclosed thermal and power challenges. Deterministic scheduling also struggles with dynamic batching and multi-tenant workloads, potentially reducing throughput.
PRO Decision
【Vendors (AMD, Intel, independent inference chip makers)】Immediately attack NVIDIA's SRAM capacity ceiling and cost trap. AMD should highlight its MI400 (expected with 3D V-Cache) scalability, showing that Infinity Fabric + HBM3e can match LPU performance on Llama 3 70B without full SRAM reliance. Intel can emphasize Gaudi 3's flexibility in dynamic batching. Cerebras should tout its Wafer-Scale Engine's 40GB+ on-chip SRAM, dwarfing NVIDIA's 230MB, and note that deterministic scheduling is native to its architecture.
【Enterprises (CIOs/architects)】Launch a zero-trust technical audit: demand NVIDIA provide end-to-end latency distributions for real LLM inference (e.g., Llama 3 70B) including tail latency from HBM fetches, not just idealized SRAM-resident numbers. Evaluate software lock-in cost: migrating from NVIDIA's hybrid stack to AMD/Intel would require CUDA rewrite and performance regression. Request SoIC packaging yield and chip lifespan data; beware of early thermal stress failures.
【Investors】See through the PR: NVIDIA's acquisition is an admission that its GPUs have inference latency flaws, and it's using expensive packaging (SoIC+1.6nm) to patch them. This will significantly raise Feynman GPU BOM cost, compressing margins. The 2028 timeline gives AMD's MI400 and Intel's Falcon Shores time to deliver more mature hybrid architectures, potentially neutralizing NVIDIA's first-mover advantage with cost disadvantages. Recommend reducing NVIDIA holdings and increasing positions in AMD and Cerebras (if IPO), as they offer superior on-chip SRAM capacity and architectural flexibility long-term.
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