Reports
AI-generated structured vendor updates
Microsoft Takes Over OpenAI's Arctic Data Center, Seizing AI Compute Control
Microsoft leases a data center in Norway's Arctic Circle from Nscale, deploying 30,000 NVIDIA Vera Rubin GPUs, filling the gap left by OpenAI's retreat. OpenAI slashes its 2030 infrastructure budget from $140B to $60B. Microsoft surpasses OpenAI in AI compute capacity and gains geographical redundancy.
Meta Invests $9.17B in Canada AI Data Center, Iris AI Chip Mass Production Begins MTIA Roadmap
Meta announced a $9.17B AI data center in Canada with 1GW capacity, and its first in-house AI chip Iris will mass produce in September, kicking off the MTIA four-generation roadmap. Meta targets 14GW compute by 2027, using 6-month chip iterations to challenge NVIDIA's annual cadence and reduce GPU dependency.
Anthropic Locks 3.5GW TPU Compute with Broadcom, Signaling Shift to Custom AI ASICs
Broadcom's Q2 FY2026 filing reveals a 3.5GW TPU compute deal with Anthropic starting 2027. This marks a strategic shift from general-purpose GPUs to custom ASICs for AI workloads, with OpenAI and Meta making similar multi-GW commitments, signaling a fundamental change in AI infrastructure.
Samsung GAIA AI PC Chip Samples with Memory-Centric NPU, Targeting 50 TOPS
Samsung launches GAIA AI PC processor with 4nm process and memory-centric NPU, integrating LPDDR5X controller with NPU for near-memory computing, achieving 40% energy efficiency improvement and 50 TOPS. Certified for Microsoft Copilot+ PC, Lenovo to adopt in Q4 2026.
AWS Sells Trainium 3 Externally, Challenging NVIDIA's AI Training Chip Dominance
AWS begins external sales of its Trainium 3 AI training chip, fabricated on TSMC 3nm process, delivering 2.52 PFLOPS per chip. Early customers include Anthropic and Uber. This move directly challenges NVIDIA's dominance and marks AWS's strategic shift from cloud provider to chip vendor.
SambaNova完成11亿美元融资估值110亿美元：推理芯片新格局确立
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TSMC Ramps PIC Capacity to 25K Wafers, CPO Silicon Photonics Poised to Disrupt AI Interconnects
TSMC plans to expand its PIC capacity to 25,000 wafers per month by 2028, with its COUPE platform becoming critical for reducing latency and power in AI systems. Initial capacity is allocated to NVIDIA, Broadcom, and AMD, marking CPO's transition from lab to mass production and accelerating the shift from electrical to optical AI interconnects.
Anthropic企业AI采用首超OpenAI 300亿年化收入运行率确认
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Cloudflare Ultimatum: Mandatory AI Crawler Separation to Control Web Data Flow
Cloudflare mandates that AI companies must separate search crawlers from AI training/agent crawlers by Sep 15, 2026, or face global blocking. It also launches Monetization Gateway and Pay Per Use, using digital fingerprinting to charge for content citation. This will reshape AI data acquisition and may worsen data scarcity.
NVIDIA Denies Kyber NVL144 Delay, But 78-Layer PCB Bottleneck Exposes AI Hardware Physics Limit
NVIDIA officially denies reports of Kyber NVL144 rack delay to 2028, but SemiAnalysis revelations about a 78-layer ultra-high-density PCB midplane bottleneck and Rubin Ultra cancellation expose hard physical limits in signal integrity and manufacturing, opening a strategic window for AMD and Google.
Anthropic Starts Custom AI Chip Development, Talks Samsung 2nm, Aims for Compute Independence
Anthropic has initiated its own AI chip development and is in talks with Samsung for 2nm foundry services. The move aims to reduce reliance on NVIDIA GPUs, optimize inference costs, and strengthen its technology moat ahead of a potential IPO. It joins OpenAI, Google, and others in the custom ASIC race, signaling a shift from software to hardware competition.
AMD Unveils Zen 6/7 CPU and MI400/500 GPU Roadmap, Targets NVIDIA Rubin with HBM4 and 2nm
AMD unveiled its Zen 6/7 CPU and MI400/500 GPU roadmap at its 2026 Financial Analyst Day, featuring TSMC 2nm process and HBM4 memory. The MI400 series boasts 432GB memory, 19.6TB/s bandwidth, and 40 PFLOPs FP4 performance, directly targeting NVIDIA's Vera Rubin architecture with an annual cadence to disrupt the AI hardware monopoly.
OpenAI Winds Down Fine-Tuning API: A Strategic Shift in AI Customization Landscape
OpenAI plans to phase out its fine-tuning API by 2027, stopping new task creation but allowing inference on existing models. This forces startups relying on fine-tuning for differentiation to migrate to open-source models or RAG, reshaping the AI customization ecosystem.
Qualcomm Enters AI Inference with Dragonfly C1000 CPU and HBC Near-Memory Compute
Qualcomm unveils Dragonfly roadmap with Oryon-based C1000 CPU and AI300 inference accelerator featuring HBC near-memory compute. Meta and Microsoft are early adopters. The strategy targets AI inference TCO reduction and memory wall breakthrough, bypassing Nvidia's training dominance.
AWS and Google Open Custom AI Chips for External Sales, ASIC Shipment Growth Surpasses GPU, TCO Inflection Point Reached
In Q2 2026, AWS Trainium and Google TPU are commercialized externally for the first time. Custom ASIC shipment growth of 44.6% surpasses GPU's 16.1%. ASIC TCO advantage reaches 40-65% for large-scale inference; Midjourney cut monthly compute cost from $2.1M to $0.7M after migrating to TPU. This marks a structural inflection point in AI compute.
OpenAI and Broadcom launch Jalapeño inference ASIC: 9-month tapeout, 2027 mass production, targets GPU replacement
OpenAI and Broadcom unveil Jalapeño, a custom inference ASIC designed in 9 months using OpenAI's own LLMs. Early benchmarks show superior performance-per-watt vs. current GPUs. Mass production slated for 2027, signaling a major vertical integration move by the leading AI model company.
Samsung Re-accelerates 1.4nm Node R&D, Adopts High-NA EUV Lithography
Samsung Electronics is re-accelerating its 1.4nm (SF1.4) process node R&D, targeting mass production by 2028-2029. It has procured High-NA EUV lithography equipment from ASML for its NRD-K R&D complex and ordered tools for 12th-gen V-NAND with wafer stacking. The move aims to catch up with TSMC and Intel in the AI chip foundry race.
Qualcomm Enters AI Datacenter with Dragonfly ARM CPU, Meta Signs Multi-Generation Deal
Qualcomm unveils Dragonfly C1000 ARM-based datacenter CPU, AI300 accelerator, and interconnect. Meta commits to multi-generation CPU supply, Microsoft Azure to deploy HBC chips. Qualcomm targets $15B+ datacenter revenue by FY2029, acquires Modular for software stack.
Qualcomm HBC Gen 1 Stacks LPDDR to 133 TB/s, Challenging HBM Dominance
Qualcomm announces HBC Gen 1, a 3D-stacked LPDDR memory with integrated compute die, achieving 133 TB/s bandwidth and 6x energy efficiency over HBM. Aimed at replacing HBM in AI accelerators, shipping with AI250 in mid-2027, but supply chain and feasibility remain uncertain.
Qualcomm Dragonfly: 250-core CPU, HBC memory, UALink interconnects target AI inference TCO
Qualcomm unveils full data center portfolio: Dragonfly C1000 250-core Oryon CPU (>5GHz, PCIe Gen7, CXL), HBC near-memory compute (133TB/s Gen1, 18x-54x effective BW), AI300 inference accelerator (UALink/ESUN scale-up), and 800G/1.6T connectivity. Multi-year Meta CPU deal. Commercial sampling 2027-2028. Targets inference TCO with tokens-per-watt leadership.