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MediaTek芯片涨价函落地全球半导体成本压力上升
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TSMC Ramps PIC Capacity to 25K Wafers, CPO Silicon Photonics Poised to Disrupt AI Interconnects
TSMC plans to expand its PIC capacity to 25,000 wafers per month by 2028, with its COUPE platform becoming critical for reducing latency and power in AI systems. Initial capacity is allocated to NVIDIA, Broadcom, and AMD, marking CPO's transition from lab to mass production and accelerating the shift from electrical to optical AI interconnects.
MediaTek and Alibaba Cloud Deploy Tongyi Qianwen LLM on Dimensity Chips
MediaTek partners with Alibaba Cloud to deploy a small version of the Tongyi Qianwen LLM on Dimensity 9300/8300 mobile platforms, enabling offline multi-turn conversations. This move aims to capture edge AI inference control via NPU optimization and SDK integration, directly challenging Qualcomm.
MediaTek Lands Exclusive Google TPU v9 Inference Upgrade Triggerfish with 2x SRAM
Google plans a TPU v9 inference upgrade, Triggerfish, exclusively fabbed by MediaTek. It features 2-3x on-chip SRAM, HBM4E DRAM, and a simulation die for local management. Production starts late 2027 with 1-2M units lifecycle, unit price ~30% higher than Humufish.
Google TPU v9 Switches to MediaTek, Breaking Broadcom's AI ASIC Monopoly
Google moves its TPU v9 Humufish design and integration contract from Broadcom to MediaTek, which handles I/O chip design and packaging. Combined with a split-foundry strategy (TSMC N2 compute, Samsung 2nm I/O), this marks a systematic effort to build a multi-vendor, multi-node supply chain, directly dismantling Broadcom's dominance in custom AI ASICs.
MediaTek Pivots to System-Level Integration: Targeting Google TPU and Musk AI Rack Deals
MediaTek elevates its AI strategy from chip design to system-level integration, targeting Google TPU PCBA L6 and Musk AI chip L10 rack assembly. Adopting a light-asset model via Taiwan's supply chain, targeting >40% gross margin, driven by rising complexity from CPO and 800V high-voltage DC power.
MediaTek Shifts from Chip Design to System Integration for Google TPU and Musk's AI Racks
MediaTek upgrades its AI strategy from chip/ASIC design to system-level integration, targeting Google TPU PCBA and Musk's AI chip rack-level (L10) work. Using an asset-light model, it leads design and validation while outsourcing manufacturing, aiming for 40-50% gross margin.
NVIDIA RTX Spark SoC Invades Windows PC: Arm CPU + GPU with 128GB Unified Memory Reshapes AI PC
At HPE Discover 2026, NVIDIA unveiled the RTX Spark SoC for Windows PCs, built on TSMC 3nm with a MediaTek-designed Arm CPU, 70B transistors, and up to 128GB unified memory. This marks NVIDIA's official entry into the PC SoC market, directly challenging Intel, AMD, and Qualcomm in the AI PC segment.
MediaTek Doubles AI ASIC Target to $2B, Challenges Broadcom in Data Center Custom Silicon
MediaTek doubles its 2026 AI ASIC revenue target to $2B, leveraging Google hyperscaler deals and the NVIDIA RTX Spark chip (featuring MediaTek's N1X Arm CPU). It aims for 10-15% of the $70-80B custom AI chip market by 2027, directly challenging Broadcom's dominance.
MediaTek Pivots from Chip Design to System-Level Integration, Targeting Google TPU and Musk AI Racks
MediaTek elevates its AI strategy from chip design to system-level integration, targeting Google TPU v10 PCBA and Musk-affiliated AI rack assembly. Using an asset-light model and Taiwan's supply chain, it aims for 40-50% gross margin in system integration.
MediaTek AI ASIC Deal with Google Reshapes Custom Silicon Landscape
MediaTek's landmark ASIC deal with Google for AI infrastructure doubles 2026 revenue target to $2B. Joint N1X CPU with Nvidia for RTX Spark AI PC and potential SpaceX/xAI orders on Intel 14A process signal a strategic pivot from consumer chips to AI custom silicon, challenging Broadcom's dominance.
NVIDIA's Triple Play: Vera CPU, N1X Laptop Chip, and $6.5B Silicon Photonics Reshape AI Infra Control
NVIDIA delivers first agent-specific Vera CPU (88 Arm v9.2 cores, 1.2TB/s memory bandwidth), teases consumer N1X laptop chip, and invests $6.5B in silicon photonics. This shifts AI orchestration control from x86 to NVIDIA's Arm ecosystem, while CPO addresses memory wall, but volume production remains challenging until post-2028.
NVIDIA and SK hynix Co-Architect Next-Gen Memory for AI Factories, Locking HBM4 to Vera Rubin
NVIDIA and SK hynix announce a multi-year tech partnership to co-develop next-gen memory for Vera Rubin, RTX Spark, and Jetson Thor. Separately, SK Telecom deploys a gigawatt-scale AI cloud using the full DGX stack, targeting 2027. This elevates SK hynix from supplier to co-architect, strengthening NVIDIA's lock-in on HBM and the AI ecosystem.
Intel's 18A Xeon 6+ and Rack Scale AI: A CPU-Centric Challenge to NVIDIA's Inference Empire
At Computex 2026, Intel launched the 18A-node Xeon 6+ processor, the Rack Scale AI platform with SambaNova's SN-50 RDU, and a fully disaggregated inference service (Vector Core Compute). This CPU-centric hybrid architecture targets agentic AI inference workloads, directly challenging NVIDIA's Vera Rubin NVL72 and GPU-dominated ecosystem.
NVIDIA RTX Spark and Nemotron-3 Ultra: AI Control Shifts from Cloud to Personal Edge
NVIDIA launched RTX Spark personal AI supercomputer (co-developed with MediaTek) and Nemotron-3 Ultra open-source model at GTC Taipei 2026. The N1X chip delivers 1 PFLOPS local AI compute, bringing LLM inference to PCs. This marks NVIDIA's pivot from cloud GPU vendor to edge AI infrastructure monopolist, redefining the PC as an AI-native device.