Reports
AI-generated structured vendor updates
TSMC Reveals Glass Substrate Plan for CoWoS, Marking Packaging Inflection
TSMC publicly disclosed its glass substrate development plan for CoWoS, partnering with Ibiden and Innolux to validate feasibility. Glass substrates offer lower signal loss and higher thermal stability than organic substrates, addressing warpage and signal integrity in large AI chip packaging. Mass production is targeted for 2027-2028, directly competing with Intel's glass substrate roadmap.
Applied Materials Launches Deposition and Etch Systems for 3D Chip Scaling
Applied Materials unveils Centris Spectral SiN ALD for uniform dielectric deposition in GAA contacts and Producer Selectra Mo Etch for molybdenum-based 3D NAND word line separation, addressing high-aspect-ratio uniformity issues critical for AI chip manufacturing.
Intel Foundry Lands Google TPU Packaging Deal: EMIB-T Shakes TSMC's AI Chip Monopoly
Intel secures a multi-billion-dollar deal to package over 3 million Google TPUs using its advanced EMIB-T 2.5D packaging, while the chips themselves remain fabricated at TSMC. This marks Intel's strategic shift from CPU vendor to second-source AI packaging partner, targeting 2028 production. Intel's 18A node yields exceed expectations, but analysts caution the scope is limited to packaging.
NVIDIA RTX Spark SoC Invades Windows PC: Arm CPU + GPU with 128GB Unified Memory Reshapes AI PC
At HPE Discover 2026, NVIDIA unveiled the RTX Spark SoC for Windows PCs, built on TSMC 3nm with a MediaTek-designed Arm CPU, 70B transistors, and up to 128GB unified memory. This marks NVIDIA's official entry into the PC SoC market, directly challenging Intel, AMD, and Qualcomm in the AI PC segment.
MediaTek Doubles AI ASIC Target to $2B, Challenges Broadcom in Data Center Custom Silicon
MediaTek doubles its 2026 AI ASIC revenue target to $2B, leveraging Google hyperscaler deals and the NVIDIA RTX Spark chip (featuring MediaTek's N1X Arm CPU). It aims for 10-15% of the $70-80B custom AI chip market by 2027, directly challenging Broadcom's dominance.
TSMC Discloses Glass Substrate Pilot, Packaging Paradigm Shifts
TSMC, with Ibiden and Innolux, publicly discloses glass substrate integration into CoWoS for advanced packaging. Glass offers superior electrical and thermal properties over organic substrates, enabling larger dies and higher density. Mass production is distant; CoPoS remains near-term priority.
ARM's Pivot to Direct AI Chip Sales: From IP Licensor to Silicon Competitor
ARM accelerates its $15B chip revenue goal by shifting from pure IP licensing to direct AI chip sales, disrupting relationships with Qualcomm and Apple, and challenging Nvidia/Intel, signaling a fundamental ecosystem restructuring.
Google Awards 3M+ TPU Packaging Orders to Intel Foundry, Breaking TSMC's CoWoS Monopoly
Google has awarded Intel Foundry over 3 million units of next-gen TPU advanced packaging orders, leveraging Intel's EMIB technology with production starting in 2028. This marks Intel Foundry's largest external customer win and a pivotal shift in AI chip packaging away from TSMC's CoWoS monopoly.
AMD Zen 6 Venice 256-Core EPYC Claims 3.3x Rack Performance Over NVIDIA Vera, But Estimates Raise Questions
AMD unveils first estimated performance of Zen 6 Venice EPYC (2nm, 256 cores), claiming 3.3x rack-level integer throughput over NVIDIA Vera at 100kW total power. A direct counter to NVIDIA's Arm push, but based on projected estimates, not silicon.
Huawei's Tao Law: LogicFolding Bypasses Lithography, 55% Density Gain on Fixed Node
At ISCAS 2026, Huawei's He Tingbo unveiled the Tao Law, replacing geometric scaling with temporal optimization targeting tau (characteristic time). LogicFolding vertically stacks active layers to shorten critical paths, achieving 55% transistor density increase and 41% energy efficiency gain on a fixed node. Kirin 2026 reaches 3.1GHz; Ascend series will adopt LogicFolding. The roadmap projects equivalent 1.4nm density by 2031, fundamentally challenging Moore's Law's lithography dependency.
TSMC Q1 Earnings: Advanced Packaging Capacity Bottleneck to Persist, Constraining AI Chip Supply Through 2025
TSMC Q1 earnings show HPC crossing 60% revenue share for the first time; CoWoS advanced packaging capacity will remain tight through 2027—the real AI chip supply bottleneck is packaging, not processes.
Intel Foundry Breakthrough: EMIB Packaging Gains Strategic Endorsement from Google, Amazon
The strategic significance of this deal far exceeds surface numbers. Google's and Amazon's simultaneous shift to Intel signals: US cloud giants' strategic consensus on 'de-TSMC-ization' in AI chips has formed. Not just chip manufacturing, but advanced packaging—high-value-added manufacturing—is also undergoing supply chain restructuring.
Apple Expands American Manufacturing Program, Bolstering Domestic AI and Sensor Supply Chains
Apple announced new partners for its American Manufacturing Program, including Bosch, Cirrus Logic, TDK, and Qnity Electronics, to shift production of critical sensors, semiconductor materials, and AI-related components to the U.S. The move involves a $400 million investment and collaborations with TSMC and GlobalFoundries to establish advanced domestic process capabilities.
TSMC Launches CyberShuttle Service to Lower Chip Verification Barriers
TSMC introduces CyberShuttle multi-project wafer service enabling shared wafer manufacturing to reduce prototype costs. The service covers advanced process nodes for early silicon validation and faster time-to-market.
TSMC Launches eFoundry Platform to Enhance Semiconductor Design Collaboration
TSMC introduces eFoundry online portal integrating design tools, IP resources, and process technology files to enhance collaboration efficiency with design customers. The platform supports advanced process design challenges through digital tools, accelerating product development from design to mass production.
TSMC Launches Mask Service to Strengthen One-Stop Chip Manufacturing
TSMC officially launches mask manufacturing service covering full process from data preparation to inspection and repair. The service integrates mask fabrication capabilities for process co-optimization and faster time-to-market. This strengthens TSMC's one-stop manufacturing solution and deepens customer collaboration.
TSMC Discloses 2nm and Beyond Technology Roadmap
TSMC announces its 2nm (N2) process will adopt GAAFET architecture replacing FinFET, with plans for subsequent A-series nodes. The technology targets performance and efficiency gains for HPC and mobile applications, leveraging new materials and 3D packaging for AI and 5G/6G demands.
TSMC Shifts to System-Level Foundry Services via Technology Platform Strategy
TSMC introduces a technology platform strategy combining advanced processes and 3D packaging to deliver customized semiconductor solutions for mobile, HPC, automotive, and IoT. This marks a shift from pure-play foundry to system-level solutions, enhancing customer lock-in and service barriers through vertical integration.
TSMC Launches Specialty Technology Platform for Diverse Applications
TSMC introduces a specialty technology platform integrating mature and specialty processes like BCD, HV, and CIS to provide customized semiconductor solutions for automotive, IoT, RF, and analog/power management applications. The platform addresses specific requirements for performance, reliability, and power efficiency across diverse use cases.
TSMC Releases Advanced Process Roadmap, N2 and A16 Technologies Lead Chip Innovation
TSMC unveiled its logic process technology roadmap, highlighting advanced nodes like N2 and A16. N2 adopts GAAFET architecture for performance and power efficiency gains, while A16 integrates backside power delivery for HPC optimization, reinforcing TSMC's leadership in semiconductor manufacturing.