ASML, TSMC, imec Demo 300mm 2D-Material Transistors at 50nm Pitch
Summary
Key Takeaways
imec, ASML, and TSMC jointly announced at the 2026 VLSI Symposium the successful integration of 2D transition metal dichalcogenide (TMD) n and pFETs on 300mm wafers, achieving a world record 50nm contacted poly pitch (CPP).
Key technical details:
- Channel materials: MoS2 for nFET, WS2 or WSe2 for pFET.
- Lithography: Single-patterning EUV optimized with ASML, enabling 28nm channel length and 50nm CPP.
- Device structure: A novel 'reverse' thin-film transistor (TFT) flow with bottom contacts and overlapping gate, transferring TMD onto pre-patterned tungsten-filled trenches.
- Performance: pFETs near record lab devices; both polarities show extremely low off-current at Vg=0V; 94% yield with Imax/Imin>10^5.
This breakthrough addresses the long-standing challenge of scaling 2D transistors while maintaining performance, enabling ultra-scaled logic, BEOL, and wafer backside applications.
Why It Matters
Beneath the surface, this is a control plane shift: traditional Si FinFET dominance by Intel, TSMC, Samsung is challenged by 2D TMD materials, breaking existing patent walls. ASML leverages EUV lithography to become the control point for TMD channel patterning, upgrading from equipment supplier to ecosystem gatekeeper.
For AI infrastructure, 2D transistors promise lower tail latency and leakage, but the announcement downplays contact resistance—shrinking CPP increases resistance, causing RC delay in high-frequency switching. The tungsten-filled trench process is incompatible with current Cu BEOL, forcing fabs into tens of billions in CapEx, ultimately passed to chip buyers. This alliance encircles Intel and Samsung: TSMC gains first-mover advantage in 2D mass production, forcing rivals to pay high EUV royalties or lag in materials.
PRO Decision
[Vendors (Intel, Samsung, GlobalFoundries)]: Immediately launch independent 2D TMD material routes, avoiding TSMC's process licensing. Invest in MoS2/WSe2 CVD growth and non-EUV patterning (e.g., nanoimprint) to bypass ASML's lock-in. Partner with equipment makers to develop Cu-compatible contact metallization.
[Enterprises (CIOs/Architects)]: Beware of technology discontinuity in chip supply chains over 3-5 years. When procuring AI accelerators, demand transistor material roadmap disclosure. Prefer multi-generational compatible packaging (Chiplet) to avoid material lock-in. Require contact resistance and RC delay data for any 2D transistor claims.
[Investors]: Distinguish long-term benefits from short-term hype. ASML and TSMC are direct winners; Intel's decline may accelerate. Monitor EUV tool orders and 2D material equipment startups (CVD/ALD). Watch for TSMC using 2D to raise foundry prices, squeezing chip designers' margins.
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