MediaTek
2026-08-12
MediaTek Targets Google TPU and Meta AI ASICs with 2nm 400G SerDes
Summary
Key Takeaways
MediaTek is advancing 400G SerDes IP development on 2nm process to extend its advanced node capabilities into data center AI ASICs, further expanding its AI chip portfolio. The company outlined a two-generation AI ASIC roadmap, widely believed to correspond to Google's TPU v8 and TPU v9 projects. The 400G SerDes IP targets the high-speed interconnect chip market, aiming for orders from Google TPU v10 and Meta AI ASICs.
On the mobile front, the Dimensity 9300 integrates the MediaTek 7th-gen AI processor APU 790 with a hardware generative AI engine, supporting LLMs from 1B to 33B parameters on-device. NeuroPilot Fusion technology boosts generative AI processing speed. MediaTek also completed deployment of Alibaba's Qwen LLM on Dimensity platforms.
Additionally, the Genio 420 platform supports real-time low-latency AI inference for LLMs under 2B parameters, reducing cloud dependency. It is pin-compatible with Genio 720/520 series and supports LPDDR4X and LPDDR5 memory. These moves show MediaTek's comprehensive push from cloud to edge AI.
Why It Matters
MediaTek's move is primarily a defensive play against Broadcom and Marvell in data center SerDes IP, while attempting to counter NVIDIA's NVLink ecosystem. However, the maturity of its 400G SerDes on 2nm is questionable given the process is not yet HVM. The IP lacks validation in real AI clusters requiring low tail latency and lossless networking, areas where Broadcom's Tomahawk and Marvell's Teralynx are proven.
Targeting Google TPU custom interconnects (e.g., ICI) may pose protocol adaptation risks if the SerDes only supports standard Ethernet. On the edge, the Dimensity + Qwen deployment faces memory bandwidth and power constraints for >10B models, limiting practical use. Genio 420's sub-2B parameter limit and pin-compatibility may restrict future scalability.
PRO Decision
【Vendors】Competitors like Broadcom and Marvell should emphasize their proven 400G SerDes deployments in large AI clusters with low latency. They should leverage open standards (UALink, InfiniBand) to limit MediaTek's proprietary lock-in. NVIDIA should open NVLink or offer standard Ethernet interconnects to counter MediaTek's differentiation.
【Enterprises】CIOs and architects should demand independent benchmarks for MediaTek's SerDes, focusing on tail latency, congestion control (PFC/ECN), and power. For custom TPU/ASIC projects, audit compatibility with existing interconnects like RoCEv2 and InfiniBand to avoid protocol lock-in. On edge AI, scrutinize real-world throughput and battery impact of 33B models on phones, favoring proven Qualcomm or Apple solutions.
【Investors】MediaTek's data center SerDes push is a long-term play, but near-term risks include 2nm ramp and customer validation. Track design wins with Google and Meta rather than PR. Edge AI deployments are largely marketing; compare MediaTek to Broadcom's stable cash flow and Marvell's data center growth before overvaluing.
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