Reports
AI-generated structured vendor updates
Etched Unveils Sohu Transformer ASIC: Claims 20x H100 Inference Throughput, Challenging NVIDIA's Grip
AI chip startup Etched emerges from stealth with Sohu, a Transformer-specific ASIC on TSMC N4P with 144GB HBM3E. By hardwiring attention mechanisms, it claims 20x throughput and 140x price-performance vs. H100 on Llama 70B. With $800M total funding and first racks shipping this summer, it directly challenges NVIDIA's inference dominance.
TSMC, ASML, imec Demonstrate 300mm 2D Material CMOS with 50nm CPP, 94% Yield
TSMC, ASML, and imec jointly demonstrated the first 300mm wafer-scale integration of 2D material transistors at VLSI 2026, achieving 50nm contacted poly pitch (CPP) for MoS₂ nFET and WS₂/WSe₂ pFET with 28nm channel length and 94% yield, marking a critical step toward industrializing 2D semiconductors.
TSMC Adds Winbond to WoW 3D Stacking Memory Supply, Breaking DRAM Oligopoly
Winbond joins TSMC's Wafer-on-Wafer (WoW) 3D stacking advanced packaging supply chain, becoming a new DRAM wafer supplier alongside Samsung, SK Hynix, and Micron. This move reduces reliance on the three global DRAM giants and strengthens AI chip packaging supply resilience. Winbond provides DRAM wafers for vertical stacking with TSMC logic wafers, offering 8GB capacity and 256GB/s bandwidth via its CUBE solution.
TSMC Bets on CoPoS and Glass Substrates: Packaging Paradigm Shifts from Wafer-Level to Panel-Level, AI Chip TCO Inflection
TSMC is replacing CoWoS with CoPoS (panel-level packaging), using 750x620mm square panels and glass core substrates, achieving 20-30% unit area cost reduction. Volume production targets 2028, with AMD Zen 7 as first key customer. This fundamentally alters AI chip packaging economics and capacity scaling.
TSMC under triple pressure: customer diversification, patent challenges, and EUV strategy shift
TSMC faces operational, legal, and commercial pressures: Google splits Icefish AI chip production with Samsung, US ITC patent probe risks import bans, and resource bottlenecks (labor, water, power) limit expansion. TSMC confirms it will skip high-NA EUV until 2029, using multi-patterning on low-NA EUV for 2nm, saving $5-10B.
TSMC Capacity Crunch Reshapes Foundry Landscape: Google, AMD, Tesla Move to Samsung for Advanced Nodes
TSMC's advanced capacity shortage through 2027 pushes Google, AMD, and Tesla to Samsung for 3nm/2nm foundry services. Samsung's 6.5% market share may see structural growth, shifting global chip supply from single-source to multi-source, though yield and trust issues persist.
TSMC Accelerates Glass Substrate CoWoS with Japanese and Taiwan Partners
TSMC partners with Ibiden and Innolux to develop glass substrates for next-gen CoWoS packaging. Simulation shows 16% warpage improvement, 27% resistance reduction, targeting AI chip performance and reliability amid competition from Intel and Samsung.
TSMC Reveals Glass Substrate Plan for CoWoS, Marking Packaging Inflection
TSMC publicly disclosed its glass substrate development plan for CoWoS, partnering with Ibiden and Innolux to validate feasibility. Glass substrates offer lower signal loss and higher thermal stability than organic substrates, addressing warpage and signal integrity in large AI chip packaging. Mass production is targeted for 2027-2028, directly competing with Intel's glass substrate roadmap.
TSMC Discloses Glass Substrate Pilot, Packaging Paradigm Shifts
TSMC, with Ibiden and Innolux, publicly discloses glass substrate integration into CoWoS for advanced packaging. Glass offers superior electrical and thermal properties over organic substrates, enabling larger dies and higher density. Mass production is distant; CoPoS remains near-term priority.
TSMC Q1 Earnings: Advanced Packaging Capacity Bottleneck to Persist, Constraining AI Chip Supply Through 2025
TSMC Q1 earnings show HPC crossing 60% revenue share for the first time; CoWoS advanced packaging capacity will remain tight through 2027—the real AI chip supply bottleneck is packaging, not processes.
TSMC 2026 Outlook: AI Demand Drives 30%+ Revenue Growth, Advanced Process and Packaging Dual Constraints
Behind TSMC's revenue growth forecast is dual logic of 'volume and price both rising': AI chip demand drives shipment growth, advanced process scarcity pushes wafer unit prices up. But A16 process delay is a signal worth watching—even TSMC faces increasing difficulty in advanced process mass production.
TSMC Discloses 2nm and Beyond Technology Roadmap
TSMC announces its 2nm (N2) process will adopt GAAFET architecture replacing FinFET, with plans for subsequent A-series nodes. The technology targets performance and efficiency gains for HPC and mobile applications, leveraging new materials and 3D packaging for AI and 5G/6G demands.
TSMC Launches Mask Service to Strengthen One-Stop Chip Manufacturing
TSMC officially launches mask manufacturing service covering full process from data preparation to inspection and repair. The service integrates mask fabrication capabilities for process co-optimization and faster time-to-market. This strengthens TSMC's one-stop manufacturing solution and deepens customer collaboration.
TSMC Launches eFoundry Platform to Enhance Semiconductor Design Collaboration
TSMC introduces eFoundry online portal integrating design tools, IP resources, and process technology files to enhance collaboration efficiency with design customers. The platform supports advanced process design challenges through digital tools, accelerating product development from design to mass production.
TSMC Launches CyberShuttle Service to Lower Chip Verification Barriers
TSMC introduces CyberShuttle multi-project wafer service enabling shared wafer manufacturing to reduce prototype costs. The service covers advanced process nodes for early silicon validation and faster time-to-market.
TSMC Launches Supplier Portal for Enhanced Supply Chain Digitalization
TSMC introduces TSMC-SUPPLY ONLINE 360, a unified online collaboration portal for its global supplier ecosystem. The platform centralizes data exchange and process integration to enhance supply chain transparency and responsiveness.
TSMC Launches Open Innovation Platform to Enhance Chip Design-Manufacturing Collaboration
TSMC introduces Open Innovation Platform® integrating process technology, IP portfolio, design tools and manufacturing expertise to provide a unified collaborative environment for chip design and manufacturing. The platform utilizes silicon-validated IP, advanced PDKs and optimized EDA flows to reduce time-to-market and improve first-time silicon success rates.
TSMC Launches Advanced Packaging Platform for Heterogeneous Integration
TSMC launches an advanced packaging platform integrating CoWoS, InFO, and SoIC 3D stacking technologies for micron-level vertical integration of chips across process nodes. It delivers higher interconnect density, bandwidth, and lower power consumption, supporting complex SoC designs as part of its Open Innovation Platform to accelerate time-to-market.
TSMC Releases Advanced Process Roadmap, N2 and A16 Technologies Lead Chip Innovation
TSMC unveiled its logic process technology roadmap, highlighting advanced nodes like N2 and A16. N2 adopts GAAFET architecture for performance and power efficiency gains, while A16 integrates backside power delivery for HPC optimization, reinforcing TSMC's leadership in semiconductor manufacturing.
TSMC Launches Specialty Technology Platform for Diverse Applications
TSMC introduces a specialty technology platform integrating mature and specialty processes like BCD, HV, and CIS to provide customized semiconductor solutions for automotive, IoT, RF, and analog/power management applications. The platform addresses specific requirements for performance, reliability, and power efficiency across diverse use cases.