Reports
AI-generated structured vendor updates
JCET's $1.4B AI Packaging Capex Reshapes Advanced Packaging Supply Chain
JCET announces $1.4B capex for AI advanced packaging in 2026, targeting Chiplet, HBM, 2.5D/3D. This marks Chinese OSAT's major entry into high-end packaging, complementing TSMC's CoWoS expansion and shifting AI packaging from Taiwan-centric to cross-strait division, supporting local hyperscalers' computing needs.
TSMC CoWoS Capacity to Reach 200k Wafers by 2027, Diversifying from GPU to CPU and ASIC
TSMC targets 200k wpm CoWoS capacity by 2027, narrowing supply-demand gap from 20% to 10%. Customer base diversifies from NVIDIA GPU to include AI server CPUs (MediaTek, AMD) and ASICs (Broadcom). CoPoS panel-level packaging enters pilot production in 2027.
TSMC Hikes Sub-7nm Prices 8-12%, Extends Lead Times to 26 Weeks, Triggering AI Chip Cost Inflation
TSMC raises sub-7nm wafer prices by 8-12% and extends lead times to 26 weeks, effective July 2026. New v2.1 directive mandates EDA tool validation for PDK access. This directly inflates AI chip TCO, delays new product launches, and solidifies TSMC's control over the AI supply chain.