Reports
AI-generated structured vendor updates
Qualcomm Dragonfly: 250-core CPU, HBC memory, UALink interconnects target AI inference TCO
Qualcomm unveils full data center portfolio: Dragonfly C1000 250-core Oryon CPU (>5GHz, PCIe Gen7, CXL), HBC near-memory compute (133TB/s Gen1, 18x-54x effective BW), AI300 inference accelerator (UALink/ESUN scale-up), and 800G/1.6T connectivity. Multi-year Meta CPU deal. Commercial sampling 2027-2028. Targets inference TCO with tokens-per-watt leadership.
AMD MI430X GPU Delivers >200 TFLOPS Native FP64, Reshaping HPC-AI Convergence Baseline
AMD powers 4 of top 10 TOP500 supercomputers and previews MI430X GPU with >200 TFLOPS native FP64. This targets AI-for-science workloads, making double-precision compute a key metric for converged HPC-AI infrastructure, directly challenging NVIDIA and Intel.
Micron-Anthropic Deal: Memory Co-Architecture Locks in AI Supply Chain
Micron and Anthropic sign a strategic agreement covering joint memory/storage architecture design, multi-year supply, Claude adoption, and investment. This ties frontier AI model demands directly to infrastructure design, aiming to optimize token economics and power efficiency, but essentially locks in supply and restructures the ecosystem.
Huawei's LogicFolding: 3D Stacking Rewrites AI Chip Rules
Huawei's Tau Scaling Law and LogicFolding architecture boost transistor density by 55% and power efficiency by 41% via vertical logic stacking, targeting 1.4nm-class by 2031. Ascend 920/910C chips are now used for DeepSeek V4-Pro post-training, signaling real-world AI workload deployment and challenging Nvidia's dominance in China.
AMD MLPerf 6.0: MI350 GPUs Achieve 3.5x Leap with MXFP4, Debut Multi-Node Training
AMD submitted its most comprehensive MLPerf Training 6.0 results, including first multi-node training (FLUX.1 on 512 GPUs) and MXFP4 training recipe. MI355X delivers 3.5x generational leap over MI300X on Llama 2-70B, within 5% of NVIDIA B200. 10 ecosystem partners validated reproducibility.
AMD and Rackspace Deploy 30MW Governed AI Stack: Ecosystem Restructuring from Silicon to Outcomes
AMD and Rackspace sign a definitive agreement to deploy 30MW of AMD AI compute (Instinct GPUs including MI355X, EPYC CPUs) across Rackspace's data centers, creating a governed enterprise AI stack with single accountability from silicon to outcomes, targeting regulated industries.
AMD Acquires MEXT: AI-Predicted Flash Nears DRAM Performance to Cut AI Memory TCO
AMD acquires MEXT, an AI-driven memory optimization startup. MEXT's predictive technology makes NAND Flash behave like DRAM, expanding effective memory capacity for AI workloads and lowering TCO. The tech will be integrated across AMD's data center portfolio (EPYC, Instinct) to address memory bottlenecks in large models.
AMD Open-Sources AI Software Stack on Vultr, Taking on NVIDIA CUDA Ecosystem
AMD launches a suite of open-source, modular enterprise AI software components on Vultr Marketplace, including AMD Inference Microservices (AIMs), AI Workbench, Resource Manager, and Solution Blueprints. This aims to provide production-grade AI infrastructure without vendor lock-in, directly challenging NVIDIA's CUDA ecosystem.
Microsoft & NVIDIA RTX Spark Brings 1 Petaflop AI to Windows, Reshaping Local Inference
At Computex 2026, Microsoft unveiled RTX Spark, an Arm-based AI superchip co-developed with NVIDIA and MediaTek, delivering up to 1 petaflop AI performance and 128GB unified memory for local 120B parameter models. Intel Arc G3 and Qualcomm Snapdragon X2 series also launched, accelerating the Windows AI PC ecosystem.
AMD, Dell, Cambridge Launch UK Sovereign AI Lab to Challenge NVIDIA's CUDA Dominance with Open ROCm
AMD, Dell, and the University of Cambridge launch the Sovereign AI Innovation Lab (SAIL) in the UK, deploying Zenith supercomputer with 5th Gen EPYC and Instinct MI355X GPUs, plus the Sunrise fusion AI system. The lab promotes open, interoperable AI infrastructure based on AMD ROCm, challenging NVIDIA's CUDA lock-in and offering long-term technology choice for national AI initiatives.
Arm's Neural Dawn: Dedicated Neural Accelerators Redefine Mobile GPU Roadmap
Arm and Sumo Digital unveil Neural Dawn, the first mobile game to use Unreal Engine MegaLights. By integrating dedicated neural accelerators into next-gen Mali GPUs, it delivers desktop-class ray-traced lighting within mobile power limits, signaling a shift from traditional to AI-native graphics pipelines.
AMD EPYC Challenges Rack-Scale Density for Agentic AI Control
AMD claims its EPYC processors lead in rack-scale performance for agentic AI's CPU-intensive services (orchestration, caching, databases). Under a 100kW rack model, EPYC 9965 'Turin' delivers 2.37x throughput over NVIDIA Vera, with next-gen 'Venice' projected at 3.30x. Emphasizes deployability on current x86 platforms, avoiding future architecture dependency.
Intel and SambaNova Rackscale AI: CPU Regains Inference Control Plane
At Computex 2026, Intel unveiled rack-scale AI infrastructure combining Xeon 6+ with SambaNova SN-50 RDUs, plus a fully disaggregated inference cloud (prefill on NVIDIA Blackwell, decode on RDUs) by Vector Core Compute. This aims to reposition the CPU as the central orchestrator for inference, challenging GPU dominance.
Intel Reclaims AI Control Plane: Xeon 6+ and E835 Target Agentic Orchestration
Intel launches Xeon 6+ (288 E-cores on 18A), E835 200GbE controllers, and Crescent Island GPU. The strategy repositions the CPU as the control plane for agentic AI orchestration and data movement, while using E835 Ethernet to standardize AI data center networking.
Cisco Scale-Across: Converged Silicon and Optics for Distributed AI Training
Cisco unveils Scale-Across architecture combining Silicon One P200 routing (51.2Tbps) and coherent pluggables (400G/800G ZR/ZR+) with open line systems, enabling deterministic low-latency, lossless connectivity for distributed AI training across data centers separated by tens of kilometers.
Cisco G300 Intelligent Packet Flow: Hardware-Accelerated AI Networking Breakthrough
Cisco launches Intelligent Packet Flow on Silicon One G300, transforming the fabric into an intelligent system with hardware-accelerated adaptive routing, collective congestion awareness, and telemetry. In 8K-16K GPU clusters, it reduces CCT by 87% vs ECMP, improves JCT by 82%, and unlocks 28% more GPU efficiency.
AMD Ryzen AI Halo & Max PRO 400: Local 300B Parameter Inference, but Hidden Lock-in and Thermal Limits
AMD launches Ryzen AI Halo developer platform (128GB unified memory, 200B parameter models) and Ryzen AI Max PRO 400 series (first x86 client to run 300B parameter models locally). Unified memory, ROCm optimization, and OEM partnerships aim to shift agentic AI from cloud to local, but shared memory bandwidth and thermal constraints limit real-world throughput.
AMD Backs SPEC CPU 2026 Benchmark, Emphasizing Open, Trusted Performance Measurement
AMD published a blog endorsing the upcoming SPEC CPU 2026 industry benchmark, emphasizing the critical role of open, reproducible CPU performance standards for customer infrastructure decisions in the AI era. The new benchmark updates its application suite and strengthens support for bare-metal cloud environments and parallel computing.
AMD and OpenAI Contribute MRC Protocol to OCP for Scalable AI Networking
AMD, in collaboration with OpenAI, Microsoft, and others, contributed the MRC (Multipath Reliable Connection) protocol, designed for large-scale AI training, to the Open Compute Project (OCP). AMD co-authored the specification and has already deployed MRC on its programmable Pensando DPU/NIC products, positioning its networking technology as a key enabler for resilient and adaptive AI infrastructure.
AMD and OpenAI Introduce MRC, a Next-Gen Transport Protocol for AI Training
AMD, in collaboration with OpenAI, Microsoft, and other industry leaders, has released the specification for the Multipath Reliable Connection (MRC) protocol. MRC addresses performance bottlenecks of RoCEv2 in hyperscale AI training clusters through intelligent packet spraying, selective retransmission, and network-signaled congestion control, aiming to improve bandwidth utilization and job resilience.