Reports
AI-generated structured vendor updates
AMD Helios Rack Challenges NVIDIA NVLink with Open UALoE Interconnect
At Advancing AI 2026, AMD launched the Helios rack with 72 MI455X GPUs, 18 Venice EPYC CPUs, and Pensando networking, claiming 30% higher inference token/$ vs NVIDIA NVL72. It introduced UALoE open interconnect to break NVLink lock-in, partnering with Cerebras, Cisco, and major AI firms.
AMD Helios Full-Stack AI Server Deployed on Azure, UALoE Open Standard Challenges NVLink
AMD and Microsoft Azure announce large-scale deployment of Helios full-stack AI servers, featuring 72 MI455X GPUs, 18 EPYC Venice CPUs, and Pensando DPUs, with 31TB HBM4 and 1.7PB/s memory bandwidth. Two new Azure VM series target Agentic AI and semiconductor design, marking Microsoft's multi-vendor strategy and challenging NVIDIA's dominance.
AMD Invests $5B in Anthropic, Secures 2GW MI450 Deployment, Reshaping AI Compute Ecosystem
AMD and Anthropic announce a strategic partnership: Anthropic will deploy up to 2GW of AMD Instinct MI450 GPUs, with AMD investing up to $5B in Anthropic. They will collaborate on ROCm optimization and Claude workload tuning, marking AMD's transition from chip vendor to AI ecosystem investor and accelerating multi-sourcing in AI compute.
NVIDIA-OpenAI $100B Partnership: 10GW Vera Rubin AI Factories Reshape Ecosystem
NVIDIA and OpenAI announce a strategic partnership to deploy at least 10GW of NVIDIA systems using the Vera Rubin platform (Rubin GPU, Vera CPU, HBM4, NVLink 6). NVIDIA will invest up to $100B. First facilities go online in H2 2026, powering OpenAI's next-gen models, marking the era of multi-GW AI factories.
AMD Unveils Zen 6 Venice, MI455X, and Helios Rack-Level Design to Challenge NVIDIA
At Advancing AI 2026, AMD launched Zen 6 EPYC Venice (2nm, up to 256 cores) and MI455X (CDNA5, 432GB HBM4, 40 PFLOPS FP4), along with Helios rack reference design (2.9 exaFLOPS FP4 per rack), claiming a 1000x AI performance roadmap, with major commitments from Meta, OpenAI, and others.
TSMC Q2净利润同比增长77%，2nm首次公开贡献收入
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NVIDIA Reveals Vera Rubin GPU and Vera CPU: 3360B Transistors, 88-Core Olympus, 10x Agentic AI Efficiency
NVIDIA fully discloses Vera Rubin GPU and Vera CPU specifications. The GPU features 3360B transistors, HBM4 288GB, and 10x agentic AI efficiency over Blackwell. The CPU has 88 custom Olympus cores, delivering 2.2x faster agentic AI performance than Intel Sapphire Rapids. This solidifies NVIDIA's full-stack strategy against x86 incumbents.
Microsoft Azure Deploys AMD Helios Rack with MI455X GPUs, Breaking NVIDIA's Cloud AI Monopoly
Microsoft Azure officially adopts AMD Helios rack-scale AI infrastructure, featuring 72 MI455X GPUs (432GB HBM4, 19.6TB/s), Venice EPYC CPUs, and Pensando DPUs. Three new instances (ND MI455X v7, HDv2, HXv2) are launched, marking Azure's shift from exclusive NVIDIA dependency to a multi-vendor AI strategy.
Intel Foundry 18A Yields Jump to 85%+; EMIB Packaging Hits 98%, Challenging TSMC N2
Intel Foundry 18A yields surged from 65% to 85%+ in a single quarter, approaching TSMC N2's 90%. EMIB advanced packaging yields reached 90-98%, turning a former bottleneck into a selling point. NVIDIA, AMD, Apple signed on but mostly as secondary suppliers.
HPE Expands Private Cloud AI with NVIDIA Vera Rubin, Enabling Agent-Native AI Factory
HPE expands its Private Cloud AI line with NVIDIA Vera Rubin NVL72 and HGX Rubin NVL8, introducing Compute XD700, Cray GX240 blade with Vera CPU, and Quantum-X800 InfiniBand. New software includes Agent Toolkit and NemoClaw for agent-native AI, with Alletra Storage MP X10000 in Q4 2026.
Huawei Atlas 950 SuperPoD & 灵衢2.0: A Systemic Pivot in China's AI Compute from Chip to Cluster
At WAIC 2026, Huawei publicly demonstrated the Atlas 950 SuperPoD, a 1024-ascend NPU card cluster, and unveiled the 灵衢2.0 high-speed interconnect protocol. This signals a strategic shift in China's AI infrastructure from single-chip to system-level leadership, creating a closed-loop ecosystem that directly challenges NVIDIA's NVL series dominance.
TSMC Pledges $100B More for 6 US Fabs, Localizing 3nm for AI Chip Supply Chain
TSMC announces an additional $100B investment in Arizona, bringing total US commitment to $265B, with plans for 6 fabs focused on 3nm and beyond. This move localizes advanced process for AI chip demand from NVIDIA, Apple, AMD, reshaping global semiconductor supply chain. Q2 net profit surged 77% YoY, FY capex raised to $60-64B.
AMD与OpenAI达成6GW算力供应历史性协议 1.6亿认股权证可获10%股权 股价盘前涨35%
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New York Enacts First Statewide AI Data Center Moratorium, Signaling Regulatory Paradigm Shift
New York State has signed an executive order imposing a one-year moratorium on AI hyperscale data centers over 50MW, effective immediately. This first statewide ban in the U.S., with 11+ states considering similar laws, signals a regulatory paradigm shift from 'build fast' to 'build steady' in AI infrastructure.
AMD Confirms Zen 6 EPYC Venice: First 2nm Server CPU Launching July 2026
AMD confirms Zen 6 EPYC Venice launch at Advancing AI 2026 (July 22-23). As the first 2nm server CPU, it features triple-core hybrid architecture, up to 192 cores, ~29% single-thread and ~22% multi-thread gains, targeting AI inference and tight CPU-GPU synergy via Infinity Fabric.
Meta Iris Chip to Mass Produce in September: 6-Month Cadence Threatens NVIDIA GPU Hegemony
Reuters confirms Meta's Iris AI chip mass production in September, targeting 2.5GW by end-2026 and 14GW by 2027. Meta's 6-month MTIA generation cadence directly challenges NVIDIA's annual GPU cycle, signaling a hyperscaler shift from GPU dependency to custom ASIC sovereignty.
JCET's $1.4B AI Packaging Capex Reshapes Advanced Packaging Supply Chain
JCET announces $1.4B capex for AI advanced packaging in 2026, targeting Chiplet, HBM, 2.5D/3D. This marks Chinese OSAT's major entry into high-end packaging, complementing TSMC's CoWoS expansion and shifting AI packaging from Taiwan-centric to cross-strait division, supporting local hyperscalers' computing needs.
TSMC CoWoS Capacity to Reach 200k Wafers by 2027, Diversifying from GPU to CPU and ASIC
TSMC targets 200k wpm CoWoS capacity by 2027, narrowing supply-demand gap from 20% to 10%. Customer base diversifies from NVIDIA GPU to include AI server CPUs (MediaTek, AMD) and ASICs (Broadcom). CoPoS panel-level packaging enters pilot production in 2027.
TSMC Hikes Sub-7nm Prices 8-12%, Extends Lead Times to 26 Weeks, Triggering AI Chip Cost Inflation
TSMC raises sub-7nm wafer prices by 8-12% and extends lead times to 26 weeks, effective July 2026. New v2.1 directive mandates EDA tool validation for PDK access. This directly inflates AI chip TCO, delays new product launches, and solidifies TSMC's control over the AI supply chain.
Intel押注3D堆叠AI芯片 18A-PT+Foveros Direct 3D+EMIB-T全栈整合
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