Reports
AI-generated structured vendor updates
TSMC CoWoS Capacity to Reach 200k Wafers by 2027, Diversifying from GPU to CPU and ASIC
TSMC targets 200k wpm CoWoS capacity by 2027, narrowing supply-demand gap from 20% to 10%. Customer base diversifies from NVIDIA GPU to include AI server CPUs (MediaTek, AMD) and ASICs (Broadcom). CoPoS panel-level packaging enters pilot production in 2027.
TSMC Bets on CoPoS and Glass Substrates: Packaging Paradigm Shifts from Wafer-Level to Panel-Level, AI Chip TCO Inflection
TSMC is replacing CoWoS with CoPoS (panel-level packaging), using 750x620mm square panels and glass core substrates, achieving 20-30% unit area cost reduction. Volume production targets 2028, with AMD Zen 7 as first key customer. This fundamentally alters AI chip packaging economics and capacity scaling.
TSMC Accelerates Glass Substrate CoWoS with Japanese and Taiwan Partners
TSMC partners with Ibiden and Innolux to develop glass substrates for next-gen CoWoS packaging. Simulation shows 16% warpage improvement, 27% resistance reduction, targeting AI chip performance and reliability amid competition from Intel and Samsung.
TSMC Discloses Glass Substrate Pilot, Packaging Paradigm Shifts
TSMC, with Ibiden and Innolux, publicly discloses glass substrate integration into CoWoS for advanced packaging. Glass offers superior electrical and thermal properties over organic substrates, enabling larger dies and higher density. Mass production is distant; CoPoS remains near-term priority.