Reports
AI-generated structured vendor updates
TSMC to Acquire AUO Panel Fabs for Panel-Level Packaging to Slash AI Chip Costs
TSMC reportedly plans to acquire two AUO panel fabs for ~$870M to boost advanced packaging for FOPLP and CoPoS. The first CoPoS line is testing at AP7, aiming to reduce cost and area waste for large AI chips by moving from circular wafers to glass panels.
TSMC CoWoS Capacity to Reach 200k Wafers by 2027, Diversifying from GPU to CPU and ASIC
TSMC targets 200k wpm CoWoS capacity by 2027, narrowing supply-demand gap from 20% to 10%. Customer base diversifies from NVIDIA GPU to include AI server CPUs (MediaTek, AMD) and ASICs (Broadcom). CoPoS panel-level packaging enters pilot production in 2027.
TSMC Bets on CoPoS and Glass Substrates: Packaging Paradigm Shifts from Wafer-Level to Panel-Level, AI Chip TCO Inflection
TSMC is replacing CoWoS with CoPoS (panel-level packaging), using 750x620mm square panels and glass core substrates, achieving 20-30% unit area cost reduction. Volume production targets 2028, with AMD Zen 7 as first key customer. This fundamentally alters AI chip packaging economics and capacity scaling.
TSMC Reveals Glass Substrate Plan for CoWoS, Marking Packaging Inflection
TSMC publicly disclosed its glass substrate development plan for CoWoS, partnering with Ibiden and Innolux to validate feasibility. Glass substrates offer lower signal loss and higher thermal stability than organic substrates, addressing warpage and signal integrity in large AI chip packaging. Mass production is targeted for 2027-2028, directly competing with Intel's glass substrate roadmap.