Reports
AI-generated structured vendor updates
Apple Launches M5 Chip Family with Enhanced AI Performance and Storage
Apple introduces M5 series chips with 4x AI performance boost, MacBook Pro standard storage increased to 1TB-2TB, and Wi-Fi 7 support. Launches entry-level MacBook Neo with fanless design and custom chips, expanding low-price market.
NVIDIA Proposes Five-Layer AI Cake Theory Defining Infrastructure Buildout Framework
NVIDIA CEO presented a five-layer AI development framework at Davos, systematically outlining full-stack construction from energy infrastructure, compute infrastructure, AI models, AI applications to industry AI factories. The framework emphasizes hierarchical synergistic development driven by generative AI, providing an ecosystem perspective for enterprise AI strategy planning.
Ericsson Defines Native Intelligence Paradigm for 6G IoT Networks
Ericsson proposes 6G massive IoT should evolve from traditional connectivity to intelligent networks with deep integration of sensing, communication and computing, supporting tens of millions of devices per km² and decades of battery life using reconfigurable intelligent surfaces and AI-native air interface.
TSMC Launches CyberShuttle Service to Lower Chip Verification Barriers
TSMC introduces CyberShuttle multi-project wafer service enabling shared wafer manufacturing to reduce prototype costs. The service covers advanced process nodes for early silicon validation and faster time-to-market.
TSMC Launches Mask Service to Strengthen One-Stop Chip Manufacturing
TSMC officially launches mask manufacturing service covering full process from data preparation to inspection and repair. The service integrates mask fabrication capabilities for process co-optimization and faster time-to-market. This strengthens TSMC's one-stop manufacturing solution and deepens customer collaboration.
TSMC Discloses 2nm and Beyond Technology Roadmap
TSMC announces its 2nm (N2) process will adopt GAAFET architecture replacing FinFET, with plans for subsequent A-series nodes. The technology targets performance and efficiency gains for HPC and mobile applications, leveraging new materials and 3D packaging for AI and 5G/6G demands.
TSMC Launches Specialty Technology Platform for Diverse Applications
TSMC introduces a specialty technology platform integrating mature and specialty processes like BCD, HV, and CIS to provide customized semiconductor solutions for automotive, IoT, RF, and analog/power management applications. The platform addresses specific requirements for performance, reliability, and power efficiency across diverse use cases.
TSMC Releases Advanced Process Roadmap, N2 and A16 Technologies Lead Chip Innovation
TSMC unveiled its logic process technology roadmap, highlighting advanced nodes like N2 and A16. N2 adopts GAAFET architecture for performance and power efficiency gains, while A16 integrates backside power delivery for HPC optimization, reinforcing TSMC's leadership in semiconductor manufacturing.
TSMC Launches Advanced Packaging Platform for Heterogeneous Integration
TSMC launches an advanced packaging platform integrating CoWoS, InFO, and SoIC 3D stacking technologies for micron-level vertical integration of chips across process nodes. It delivers higher interconnect density, bandwidth, and lower power consumption, supporting complex SoC designs as part of its Open Innovation Platform to accelerate time-to-market.
TSMC Launches Open Innovation Platform to Enhance Chip Design-Manufacturing Collaboration
TSMC introduces Open Innovation Platform® integrating process technology, IP portfolio, design tools and manufacturing expertise to provide a unified collaborative environment for chip design and manufacturing. The platform utilizes silicon-validated IP, advanced PDKs and optimized EDA flows to reduce time-to-market and improve first-time silicon success rates.
Google Launches Mid-Range Pixel 10a with Enhanced AI Photography and Durability
Google launched the Pixel 10a smartphone, featuring its Tensor G4 chip and AI photography tools, focused on durability and mid-market positioning. This continues Google's strategy of integrating hardware and AI for differentiation, without enterprise-level architectural changes.
Ericsson and Intel Collaborate on AI-Native 6G Network Architecture
Ericsson and Intel announced a strategic collaboration to develop AI-native 6G network architecture and air interface. The partnership integrates Intel's hardware platforms with Ericsson's wireless expertise to embed AI at the network foundation. This aims to enhance network performance, efficiency, and automation for commercial deployment around 2030.
AT&T and Ericsson Deploy AI-Native Software for Cloud RAN Optimization
AT&T and Ericsson deployed AI-native software on Intel Xeon 6 SoC to enhance Cloud RAN performance through real-time analysis and intelligent scheduling. The solution leverages integrated AI acceleration to dynamically optimize network capacity and energy efficiency, supporting AT&T's transition to open programmable network architecture.
Huawei Releases AI-Native Data Center Networking Solution Galaxy AI Fabric 2.0
Huawei launched Galaxy AI Fabric 2.0 data center networking solution with AI-Native architecture for autonomous networking. It includes self-developed Solar 5.0 chip switches, iLossless 3.0 algorithm, and intelligent management platform, supporting 10,000-card AI clusters.
TSMC Advances AI Hardware Innovation with Advanced Process and 3D Packaging
TSMC reveals AI technology research progress, focusing on N3/N2 advanced nodes and 3D Fabric heterogeneous integration. It enhances AI chip performance and efficiency through optimized transistor architecture and packaging, targeting memory bandwidth bottlenecks for cloud-to-edge AI applications.
TSMC Launches Interconnect Platform to Strengthen Chip Design Ecosystem
TSMC introduces an Interconnect technology platform integrating advanced packaging, 3D IC, and interconnect materials, offering end-to-end design-to-manufacturing solutions. The platform provides design rules, electro-thermal models, and verified IP libraries to optimize signal integrity, power integrity, and thermal management, reducing design cycles and development risks.
Apple Launches Entry-Level MacBook Neo to Strengthen On-Device AI Deployment
Apple introduces the $599 MacBook Neo with its A18 Pro chip, claiming 3x faster on-device AI processing than x86 PCs. The device integrates Apple Intelligence and macOS Tahoe, representing Apple's strategy to expand into mainstream pricing with custom silicon.
Huawei All-Flash Storage Passes ESG Validation with Performance and AI Ops
Huawei's OceanStor Dorado all-flash storage passed ESG validation, confirming advantages in performance, efficiency, and reliability. It uses FlashLink® 3.0 architecture and smart chips for microsecond latency and 21M IOPS, with integrated AI for intelligent operations.
TSMC Forms 3DFabric Alliance to Advance Packaging Ecosystem
TSMC establishes the 3DFabric Alliance to integrate partners across EDA tools, IP, design services, and manufacturing packaging, accelerating system-level innovation. The alliance leverages TSMC's 3D silicon stacking and advanced packaging technologies to provide validated design flows, reducing time-to-market and enhancing its system integration capabilities for HPC and AI chips.
TSMC Forms Cloud Alliance to Drive Semiconductor Design to Cloud
TSMC partners with cloud providers, EDA vendors and design services to form Open Innovation Platform Cloud Alliance, building a verified cloud design solution framework. The alliance will optimize EDA tool efficiency in cloud environments and provide TSMC process-certified reference flows.