Reports
AI-generated structured vendor updates
NVIDIA Invests $2B with Lumentum to Advance AI Optical Interconnect Technology
NVIDIA invests $2 billion in Lumentum to jointly develop advanced optical interconnect technology for AI factories. The partnership aims to overcome chip-to-chip communication bottlenecks in large-scale GPU clusters, improving energy efficiency and scalability for systems like NVL72.
NVIDIA Vera Rubin NVL72 Enters Production, 10x Energy Efficiency Reshapes AI Infrastructure
NVIDIA has announced full production of the Vera Rubin NVL72 platform, with first shipments to CoreWeave, Microsoft, Amazon, and Oracle. Each rack integrates 72 Rubin GPUs and 36 Vera CPUs, delivering 10x improvement in energy efficiency and inference cost over Blackwell for agentic AI workloads, marking a new era of rack-scale AI infrastructure.
NVIDIA-OpenAI $100B Partnership: 10GW Vera Rubin AI Factories Reshape Ecosystem
NVIDIA and OpenAI announce a strategic partnership to deploy at least 10GW of NVIDIA systems using the Vera Rubin platform (Rubin GPU, Vera CPU, HBM4, NVLink 6). NVIDIA will invest up to $100B. First facilities go online in H2 2026, powering OpenAI's next-gen models, marking the era of multi-GW AI factories.
TEST 2026-07-23 DailyShift 24h信号测试
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NVIDIA Reveals Vera Rubin GPU and Vera CPU: 3360B Transistors, 88-Core Olympus, 10x Agentic AI Efficiency
NVIDIA fully discloses Vera Rubin GPU and Vera CPU specifications. The GPU features 3360B transistors, HBM4 288GB, and 10x agentic AI efficiency over Blackwell. The CPU has 88 custom Olympus cores, delivering 2.2x faster agentic AI performance than Intel Sapphire Rapids. This solidifies NVIDIA's full-stack strategy against x86 incumbents.
Microsoft and Mistral Partner to Build Sovereign AI Infrastructure for Regulated European Industries
Microsoft and Mistral expand their partnership with a multi-billion dollar deal. Mistral gains thousands of NVIDIA Vera Rubin GPUs and integrates its Medium 3.5 and OCR 4 models into Microsoft Foundry and Copilot Studio, offering cloud, connected, and offline deployment modes for European regulated industries under EU AI Act.
NVIDIA Spectrum-6 102.4Tbps Switch Goes Commercial, Cisco Adoption Confirms Bandwidth Inflection
NVIDIA announces Spectrum-6 102.4Tbps Ethernet switch for AI factories, doubling bandwidth with CPO and liquid cooling. Cisco confirms adoption in N9100 series, while Broadcom launches Tomahawk 6, signaling a terabit Ethernet race for AI infrastructure.
Google's Frozen v2 Chip Hardwires Gemini Architecture for 6-10x TPU Efficiency, Set for 2028
Google is developing Frozen v2, a dedicated AI chip that hardwires the Gemini model architecture into silicon for 6-10x energy efficiency per token over current TPUs. It is a new product line, planned for 2028, with weight update flexibility but a frozen architecture. This validates the industry shift from general-purpose GPUs to dedicated ASICs for AI inference.
Huawei Ascend 950 Supernode: Self-Developed HCCS Interconnect for Sovereign AI Compute Ecosystem
Huawei unveiled the Ascend 950 Supernode at WAIC, integrating 32 self-developed Ascend 950 AI processors with HCCS high-speed interconnect, achieving 2.5x compute density and supporting trillion-parameter model training, offering a sovereign AI compute alternative free from overseas supply chains.
Huawei Atlas 950 SuperPoD & 灵衢2.0: A Systemic Pivot in China's AI Compute from Chip to Cluster
At WAIC 2026, Huawei publicly demonstrated the Atlas 950 SuperPoD, a 1024-ascend NPU card cluster, and unveiled the 灵衢2.0 high-speed interconnect protocol. This signals a strategic shift in China's AI infrastructure from single-chip to system-level leadership, creating a closed-loop ecosystem that directly challenges NVIDIA's NVL series dominance.
AMD与OpenAI达成6GW算力供应历史性协议 1.6亿认股权证可获10%股权 股价盘前涨35%
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IBM Unveils 0.7nm Nanostack 3D Transistor, Doubling Density and Extending Moore’s Law
IBM debuts the world’s first sub-1nm chip technology at 0.7nm node using a nanostack 3D transistor architecture, packing nearly 100 billion transistors with double the density of its 2nm node. It delivers 50% performance gain or 70% energy efficiency improvement, and 40% SRAM scaling for AI workloads.
AMD Confirms Zen 6 EPYC Venice: First 2nm Server CPU Launching July 2026
AMD confirms Zen 6 EPYC Venice launch at Advancing AI 2026 (July 22-23). As the first 2nm server CPU, it features triple-core hybrid architecture, up to 192 cores, ~29% single-thread and ~22% multi-thread gains, targeting AI inference and tight CPU-GPU synergy via Infinity Fabric.
NVIDIA's HVDC Power Shift Reshapes AI Data Center Energy Efficiency and Supply Chain
NVIDIA is driving a shift from AC to HVDC power systems for AI data centers, aiming to reduce conversion losses and improve efficiency. This move will reshape the entire supply chain for servers, power equipment, and cooling, but faces challenges in safety and standardization. It signals a generational change in AI infrastructure power delivery.
Samsung GAIA AI PC Chip Samples with Memory-Centric NPU, Targeting 50 TOPS
Samsung launches GAIA AI PC processor with 4nm process and memory-centric NPU, integrating LPDDR5X controller with NPU for near-memory computing, achieving 40% energy efficiency improvement and 50 TOPS. Certified for Microsoft Copilot+ PC, Lenovo to adopt in Q4 2026.
AWS boosts Trainium 3 shipments, accelerating ASIC substitution for NVIDIA GPUs
Supply chain sources indicate Amazon AWS has instructed vendors to increase Trainium 3 shipments for Q3 2026 by 20-30%. This signals strong confidence in its custom ASIC strategy to reduce dependence on NVIDIA GPUs, leveraging superior cost and power efficiency for cloud AI training.
Huawei Unveils Tao's Law V2: Kirin 2026 Boosts AI Inference 40% on Same Node
Huawei's He Tingbo releases Tao's Law V2, detailing Kirin 2026 metrics: 238 MTr/mm² transistor density (+55%), 41% power reduction at iso-performance, and 40% SRAM frequency increase. Without EUV lithography, co-optimization of architecture, circuit, and process delivers equivalent performance gains, proving system-level optimization as a viable alternative to Moore's Law scaling.
AMD Unveils Zen 6/7 CPU and MI400/500 GPU Roadmap, Targets NVIDIA Rubin with HBM4 and 2nm
AMD unveiled its Zen 6/7 CPU and MI400/500 GPU roadmap at its 2026 Financial Analyst Day, featuring TSMC 2nm process and HBM4 memory. The MI400 series boasts 432GB memory, 19.6TB/s bandwidth, and 40 PFLOPs FP4 performance, directly targeting NVIDIA's Vera Rubin architecture with an annual cadence to disrupt the AI hardware monopoly.
Anthropic in talks with Samsung for 2nm AI chip, targeting NVIDIA CUDA control shift
Anthropic is in early talks with Samsung to manufacture custom AI chips using 2nm process and advanced packaging, hiring ex-OpenAI chip engineer Clive Chan. This aims to reduce NVIDIA GPU dependency and seize control of AI infrastructure, signaling a control plane shift in AI compute.
Qualcomm Enters AI Inference with Dragonfly C1000 CPU and HBC Near-Memory Compute
Qualcomm unveils Dragonfly roadmap with Oryon-based C1000 CPU and AI300 inference accelerator featuring HBC near-memory compute. Meta and Microsoft are early adopters. The strategy targets AI inference TCO reduction and memory wall breakthrough, bypassing Nvidia's training dominance.