Reports
AI-generated structured vendor updates
Huawei unveils Atlas 950 SuperPoD: 1024-card memory-coherent AI supernode
Huawei unveiled the Atlas 950 SuperPoD at WAIC 2026, powered by the 950DT chip, supporting 1024 interconnected cards with 256TB unified memory addressing. Designed for trillion-parameter model training and Agentic AI inference, it marks a shift from chip-level stacking to system-level unified architecture.
Huawei Atlas 950 SuperPoD & 灵衢2.0: A Systemic Pivot in China's AI Compute from Chip to Cluster
At WAIC 2026, Huawei publicly demonstrated the Atlas 950 SuperPoD, a 1024-ascend NPU card cluster, and unveiled the 灵衢2.0 high-speed interconnect protocol. This signals a strategic shift in China's AI infrastructure from single-chip to system-level leadership, creating a closed-loop ecosystem that directly challenges NVIDIA's NVL series dominance.
Huawei Ascend 950 SuperPoD: 1024 NPUs with 256TB Unified Memory Redefines AI Compute
Huawei unveiled the Ascend 950 SuperPoD at WAIC 2026, featuring 1024 NPUs per cabinet with 256TB unified memory and 3μs latency. This system-level innovation compensates for process limitations, scaling to 500,000 NPUs for trillion-parameter model training, shifting the compute race from single-chip to system efficiency.
Huang Denies Vera Rubin Delay; NVIDIA Defends AI Compute Throne
Jensen Huang officially denies rumors of a delay for the Vera Rubin platform, stating it is already in production and on track for mass deployment. This move aims to quell market anxiety over NVIDIA's product roadmap and solidify its leadership in AI training and inference chips.
AMD与OpenAI达成6GW算力供应历史性协议 1.6亿认股权证可获10%股权 股价盘前涨35%
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NVIDIA Debuts T3000/T2000 Modules and Cosmos 3 Edge, Builds Sovereign AI Ecosystem in Japan
NVIDIA unveils T3000/T2000 compute modules (Thor architecture) and Cosmos 3 Edge world model, signs Japan Noetra alliance for 13,750 Vera CPUs + 27,500 Rubin GPUs (140MW). Sovereign AI revenue triples to $30B+ in FY2026, accelerating the physical AI ecosystem.
IBM Unveils 0.7nm Nanostack 3D Transistor, Doubling Density and Extending Moore’s Law
IBM debuts the world’s first sub-1nm chip technology at 0.7nm node using a nanostack 3D transistor architecture, packing nearly 100 billion transistors with double the density of its 2nm node. It delivers 50% performance gain or 70% energy efficiency improvement, and 40% SRAM scaling for AI workloads.
NVIDIA and Nokia Launch Commercial AI-RAN: GPU-Defined RAN Replaces Purpose-Built Hardware
NVIDIA and Nokia announce the first commercial AI-RAN platform, built on Nokia's anyRAN software and NVIDIA's Aerial AI-RAN stack. It achieves over 20% spectrum efficiency gain via AI-driven radio innovations, targeting 100%+ by 2028. The platform aims to shift RAN from purpose-built hardware to a software-defined, GPU-based compute model.
Apple in Talks with PrismML to Compress Qwen 27B Model 15x for On-Device AI
Apple is negotiating with AI startup PrismML to deploy a compressed version of Alibaba's Qwen 27B parameter model on iPhone. PrismML's compression technology reduces memory usage by 15x, enabling 27B models to run locally with 10GB VRAM, shifting Apple's AI strategy from cloud-dependent to on-device inference.
CrowdStrike Integrates Claude API, Elevates AI Agent Security to SOC Core
CrowdStrike integrates Anthropic's Claude Compliance API into its Falcon platform, enabling unified monitoring of Claude Enterprise and Platform activities in its Next-Gen SIEM, correlated with endpoint, identity, and cloud telemetry for automated AI agent security response.
Cisco, Aliro, zerothird Demo Operational QKD Network with MACsec
Cisco, Aliro, and zerothird demonstrated an operational entanglement-based QKD network at Cisco Photonics Center. Aliro Orchestrator manages quantum key distribution, feeding keys via Cisco SKIP interface into Cisco 8000 routers for MACsec encryption, marking a transition from lab to production.
AMD Confirms Zen 6 EPYC Venice: First 2nm Server CPU Launching July 2026
AMD confirms Zen 6 EPYC Venice launch at Advancing AI 2026 (July 22-23). As the first 2nm server CPU, it features triple-core hybrid architecture, up to 192 cores, ~29% single-thread and ~22% multi-thread gains, targeting AI inference and tight CPU-GPU synergy via Infinity Fabric.
Intel Launches Starfire Space-Grade SoC on 18A to Challenge Xilinx Dominance
Intel unveils Starfire, a space-grade SoC built on Intel 18A process with Foveros packaging, derived from Panther Lake. Targeting satellite payloads and on-orbit AI inference, sampling in Q3 2026, it aims to disrupt Xilinx/Microchip's space FPGA ecosystem with advanced AI and SWaP-C optimization.
NVIDIA's HVDC Power Shift Reshapes AI Data Center Energy Efficiency and Supply Chain
NVIDIA is driving a shift from AC to HVDC power systems for AI data centers, aiming to reduce conversion losses and improve efficiency. This move will reshape the entire supply chain for servers, power equipment, and cooling, but faces challenges in safety and standardization. It signals a generational change in AI infrastructure power delivery.
TSMC CoWoS Capacity to Reach 200k Wafers by 2027, Diversifying from GPU to CPU and ASIC
TSMC targets 200k wpm CoWoS capacity by 2027, narrowing supply-demand gap from 20% to 10%. Customer base diversifies from NVIDIA GPU to include AI server CPUs (MediaTek, AMD) and ASICs (Broadcom). CoPoS panel-level packaging enters pilot production in 2027.
WhiteFiber and DriveNets Achieve 111.2 Tbps Cross-DC AI Fabric, Breaking Power Constraints
WhiteFiber announces Project Redwood, partnering with DriveNets Ethernet AI fabric (FSE, VOQ, deep buffers), WEKA storage, and NVIDIA H200 GPUs, achieving 111.2 Tbps bandwidth and 0.9ms latency over 83km dark fiber, treating two geographically separated GPU clusters as a single logical supercluster. Commercialization planned for Q3 2026.
Intel押注3D堆叠AI芯片 18A-PT+Foveros Direct 3D+EMIB-T全栈整合
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PrismML's 1-bit Compression: 27B Qwen Model Runs Fully on iPhone 17 Pro in 4GB
PrismML compressed a 27B-parameter dense LLM (Qwen 3.6) to 4GB, running fully on iPhone 17 Pro. Using native 1-bit quantization (weights as {-1, +1}), it achieves >92% compression, 8x faster inference, and 75-80% energy reduction. This challenges Apple's sparse architecture, potentially shifting edge AI from cloud-reliant to device-native.
Huawei Ascend 10K-Card Cluster Goes Live, UnifiedBus Protocol Pools All Resources
Huawei launched an Ascend 10,000-card AI cluster in Shaoguan, Guangdong, and showcased the Atlas 950 SuperPoD with its proprietary UnifiedBus interconnect supporting 8,192 NPUs at 16.3 PB/s. Huawei Cloud also entered the Gartner 2026 Cloud AI Infrastructure Leaders quadrant, reinforcing its push for a self-contained AI ecosystem.
Samsung GAIA AI PC Chip Samples with Memory-Centric NPU, Targeting 50 TOPS
Samsung launches GAIA AI PC processor with 4nm process and memory-centric NPU, integrating LPDDR5X controller with NPU for near-memory computing, achieving 40% energy efficiency improvement and 50 TOPS. Certified for Microsoft Copilot+ PC, Lenovo to adopt in Q4 2026.