Reports
AI-generated structured vendor updates
AMD Confirms Zen 6 EPYC Venice: First 2nm Server CPU Launching July 2026
AMD confirms Zen 6 EPYC Venice launch at Advancing AI 2026 (July 22-23). As the first 2nm server CPU, it features triple-core hybrid architecture, up to 192 cores, ~29% single-thread and ~22% multi-thread gains, targeting AI inference and tight CPU-GPU synergy via Infinity Fabric.
TSMC CoWoS Capacity to Reach 200k Wafers by 2027, Diversifying from GPU to CPU and ASIC
TSMC targets 200k wpm CoWoS capacity by 2027, narrowing supply-demand gap from 20% to 10%. Customer base diversifies from NVIDIA GPU to include AI server CPUs (MediaTek, AMD) and ASICs (Broadcom). CoPoS panel-level packaging enters pilot production in 2027.
英特尔确认上调部分消费级和服务器CPU价格，数据中心产品涨幅达数百美元
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NVIDIA Vera CPU Threatens x86: 1.5x Performance, 4x Density, Full-Stack AI Lock-In
Rumors indicate NVIDIA will unveil its first general-purpose CPU Vera at Computex 2026, claiming 1.5x x86 performance, 2x throughput, and 4x rack density. Shipment targets: 1.2M units in FY2027, 4.2M in FY2028. Vera targets the AI inference shift from 1:8 to 1:1 CPU/GPU ratio, complementing Grace to create a full GPU+CPU stack.
AI Agent Workloads Trigger Structural CPU Shortage, Arm and AMD Reshape Server Value Chain
AI inference and agent orchestration surge CPU demand, shifting CPU-GPU ratio from 1:8 to 1:1. AMD EPYC lead time 8-12 weeks, Intel Xeon up to 6 months; Arm's 3nm 136-core AGI processor co-developed with Meta/Cerebras/Cloudflare/OpenAI sees demand exceeding 200 billion USD. CPU replaces GPU as the new AI infrastructure bottleneck, with Arm and AMD reshaping the value chain.
AMD Highlights CPU's Critical Role in Agentic AI Orchestration and Inference
AMD states Agentic AI workloads require serial decision-making and context management, better suited for CPUs. The company emphasizes high-core-count, high-memory-bandwidth server CPUs will lead in agent orchestration and lightweight inference, complementing GPUs in training. This signals a strategic repositioning of CPUs in AI data center architecture.