On July 6, 2026, SemiAnalysis disclosed that NVIDIA's Kyber NVL144 rack architecture has been delayed by over 12 months to 2028 due to PCB midplane manufacturing bottlenecks, with backup plan NVL72x2 cancelled and the 4-chip Rubin Ultra variant scrapped. Meanwhile, Huawei's CloudMatrix 384 supernode has been deployed in over 300 installations, achieving full peer-to-peer interconnect across 384 Ascend NPUs.
The comparison between these two technical paths reveals a core contradiction: NVIDIA pursues peak single-chip performance but hits physical manufacturing walls, while Huawei, constrained in per-chip compute, achieves supernode mass production through system-level innovation. The battle for AI infrastructure scale-up is shifting from chip performance competition to a systemic contest of engineering and manufacturing capability.
Key Technical Comparison:
| Dimension | NVIDIA | Huawei |
|---|---|---|
| Largest validated scale domain | 72 GPU (NVL72) | 384 NPU (CloudMatrix 384) |
| Next-gen target | 144 GPU (NVL144) → 2028 | 8,192 cards (Atlas 950) → 2026 Q4 |
| Interconnect technology | NVLink → PCB midplane (stuck) → CPO (not ready) | Unified Bus (in production) |
| Memory architecture | HBM bound to GPU | 48TB global memory pooling |
| Per-chip performance | Industry-leading (Rubin GPU FP4 50 PFLOPS) | ~40-60% of NVIDIA per chip |
| Ecosystem openness | NVLink/CUDA closed | Unified Bus partially open-sourced (5 components) |
Huawei's approach is fundamentally different: rather than pursuing extreme per-chip performance, it achieves system-level compute aggregation through full peer-to-peer interconnect architecture. The CloudMatrix 384 uses Unified Bus protocol for full peer-to-peer non-blocking interconnect across 384 Ascend NPUs with 784GB/s bandwidth (15x improvement), nanosecond-level latency, and 48TB global memory pooling through EMS (Elastic Memory Storage).
Huawei's Tao's Law V2 provides theoretical backing at the system level: the fourth layer of τ optimization targets end-to-end transmission latency compression through Unified Bus and unified memory addressing — the precise technology path implemented in CloudMatrix.
Competitive Implications:
NVIDIA faces an 18-month competitive window gap. SemiAnalysis explicitly stated that NVIDIA has "no validated solution to scale up Rubin Ultra's scale-up domain," leaving room for AMD MI500X or TPUv8i Broadfly to surpass it.
Huawei's Atlas 950 SuperPod (8,192 cards) will debut at WAIC 2026 (July 17-20) with Q4 shipment. If delivered on schedule, it will establish an order-of-magnitude advantage in supernode scale domain.
However, Huawei faces challenges: per-chip efficiency gap (384 NPUs consume ~2.5x the power of equivalent NVIDIA GB200 NVL72), CUDA ecosystem lock-in, and geopolitical market access restrictions.
Why it Matters
Supernode scale-up domain is becoming a new competitive dimension for AI compute. NVIDIA's PCB midplane predicament demonstrates that system-level engineering capability is as critical as chip design — when system complexity exceeds manufacturing limits, vertical integration becomes a single point of failure. Huawei's achievement of supernode mass production through Tao's Law system-level τ optimization (Unified Bus + unified memory addressing) shows that system-level innovation can overcome per-chip constraints. This shift directly impacts enterprise compute procurement strategies over the next 18 months and NVIDIA's ability to deliver on its 'AI Computing Partner' narrative.
DECISION
- For Vendors: Immediately evaluate supernode scale-up domain technology positioning. NVIDIA's PCB midplane issue is not an isolated case — when system complexity exceeds manufacturing limits, any vendor faces similar risks. Investing in system-level engineering and manufacturing process validation should be equal priority to chip design.
- For Enterprise Customers: Monitor NVIDIA NVL144 progress and AMD MI400 scale-up plans. NVL72 remains the mature NVIDIA option short-term, but evaluate alternatives during the 18-month window. Huawei CloudMatrix 384 is a validated choice in the China market.
- For Investors: NVIDIA's current TTM P/E ratio is ~29.84x, below its 5-year median of 59.57x. The valuation discount partially reflects product uncertainty, but NVL144 delay + Rubin Ultra downsizing may further compress growth expectations. Watch Q3 earnings for Rubin shipment cadence and management commentary on NVL144 timeline.
PREDICT
- Within 12 months: NVIDIA will deliver Rubin NVL72 on schedule (Fall 2026), but NVL144 delay will continue to impact market expectations for ultra-large-scale training. AMD MI400 will announce scale-up plans to fill the gap.
- Within 2 years: CPO NVSwitch readiness on the Feynman platform is the critical validation node for NVIDIA's supernode roadmap. If Huawei Atlas 950 SuperPod (8,192 cards) delivers on schedule, it will establish an order-of-magnitude advantage in scale domain.
- Within 3 years: The supernode battle will shift AI infrastructure competition from 'per-chip performance' to 'systems engineering capability.' The upstream supply chain for PCB/CCL/CPO will be fundamentally reshaped. If Tao's Law system-level optimization path is validated for AI accelerators, it will alter the basic framework of global compute competition.
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