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NVIDIA
2026-06-24
Technology Integration Impact: Major Conf: 92%

China's LineShine Tops TOP500: CPU-Only 2.2 ExaFLOPS with ARMv9 and HBM Memory

Summary

LineShine supercomputer achieves 2.198 ExaFLOPS FP64 sustained using 13.79 million ARMv9 cores across 20,480 nodes, making it the first system to exceed 2 ExaFLOPS without GPUs. Each node has dual LX2 CPUs (304 cores) with 32GB HBM, demonstrating a CPU+HBM architecture breakthrough for HPC.

Key Takeaways

According to the June TOP500 list, China's LineShine ranks #1 with 2.198 ExaFLOPS HPL sustained (peak 2.736 ExaFLOPS, ~80% efficiency). It uses only CPUs—no GPUs or accelerators—for FP64. The system comprises 13.79 million ARMv9 cores across 20,480 nodes, each with dual LX2 CPUs (304 cores total) and 32GB HBM per CPU. HBM provides fast access, then offloads to DDR5 (~256GB per CPU). Each CPU has two dies, each with four NUMA domains (38 cores @1.55 GHz, 4GB HBM). Total power: 42.2 MW, efficiency: 52.07 GigaFLOPS/Watt. It's the only CPU-only exascale system, quadrupling Fugaku's performance.

Why It Matters

LineShine's CPU-only design is a strategic move to bypass x86/GPU supply chains, but it hides critical engineering limitations:

  • NUMA complexity: 8 NUMA domains per CPU cause severe cross-domain latency, reducing real-world efficiency below HPL's 80% for irregular workloads.
  • HBM capacity trap: Only 32GB HBM per CPU forces frequent offloads to DDR, creating tail latency and bandwidth bottlenecks for memory-bound HPC applications.
  • Efficiency gap: 52.07 GigaFLOPS/Watt trails GPU systems (e.g., Frontier ~60). The 42.2 MW power draw poses deployment challenges. The report omits application performance degradation and NUMA tuning costs.

PRO Decision

【Vendors】Competitors (NVIDIA, Intel, AMD) should:

  • NVIDIA: Benchmark real HPC workloads (HPCG, HPL-AI) to expose LineShine's NUMA latency and tail latency vs. GPU systems.
  • Intel: Highlight ARMv9's software immaturity and promote Xeon Max (HBM) as a more proven CPU+HBM solution.
  • AMD: Compare MI300A APU's unified memory to avoid LineShine's HBM→DDR offload bottleneck.

【Enterprises】CIOs/architects: Conduct zero-trust audits demanding non-HPL benchmarks (OpenFOAM, WRF) with NUMA-aware tuning. Assess vendor lock-in risk of LX2/ARMv9; prefer open standards or mainstream x86/GPU.
【Investors】See through political narrative: LineShine is a state-driven project, not a commercial breakthrough. Focus on its 42.2 MW power cost and operational complexity. Stay cautious on ARM HPC until independent validation.

Source: Techpowerup
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